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2022-11-22soc: ti: k3-socinfo: Add AM62Ax JTAG IDVignesh Raghavendra1-0/+1
Add JTAG ID entry to help identify AM62Ax SoC in kernel. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221119152447.241166-1-vigneshr@ti.com
2022-11-22Merge tag 'v6.1-next-soc' of ↵Arnd Bergmann4-151/+153
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/drivers mmsys: - add support for MT8186 - add correct compatible solution for vdosys[0,1] on MT8195 pmic wrapper: - add support for MT8365 * tag 'v6.1-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: Add deprecated compatible to mmsys soc: mediatek: pwrap: add mt8365 SoC support soc: mediatek: pwrap: add support for sys & tmr clocks dt-bindings: soc: mediatek: pwrap: add MT8365 SoC bindings soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0" dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func Link: https://lore.kernel.org/r/cc756001-a942-90b0-b79d-62c1fc189828@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-22Merge tag 'tegra-for-6.2-soc-v2' of ↵Arnd Bergmann9-424/+1073
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v6.2-rc1 In addition to a number of improvements and cleanups this contains a fix for the FUSE access on newer chips, adds Tegra234 I/O pad support and fixes various issues with wake events. The SoC sysfs revision attribute is updated to include the platform information so drivers can check for silicon vs. pre-silicon, among other things. * tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Remove redundant dev_err call soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_err firmware: tegra: include IVC header file only once soc/tegra: cbb: Check firewall before enabling error reporting soc/tegra: cbb: Add checks for potential out of bound errors soc/tegra: cbb: Update slave maps for Tegra234 soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194 soc/tegra: fuse: Use platform info with SoC revision soc/tegra: pmc: Process wake events during resume soc/tegra: pmc: Fix dual edge triggered wakes soc/tegra: pmc: Add I/O pad table for Tegra234 soc/tegra: fuse: Add nvmem keepout list soc/tegra: fuse: Use SoC specific nvmem cells soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY Link: https://lore.kernel.org/r/20221121171239.2041835-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-22Merge tag 'riscv-soc-for-v6.2-mw0' of ↵Arnd Bergmann1-8/+25
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.2 SiFive: - add probe error handling to the ccache driver * tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init() soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init() soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() Link: https://lore.kernel.org/r/Y3u0Oydiv2Wauda2@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21soc: mediatek: Add deprecated compatible to mmsysMatthias Brugger1-0/+4
For backward compatibility we add the deprecated compatible. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221111082912.14557-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21soc: mediatek: pwrap: add mt8365 SoC supportFabien Parent1-0/+78
Add PMIC Wrap support for MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221031093401.22916-4-fchiby@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21soc: mediatek: pwrap: add support for sys & tmr clocksFabien Parent1-4/+32
MT8365 requires an extra 2 clocks to be enabled to behave correctly. Add support these 2 clocks, they are made optional since they seem to be present only on MT8365. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221031093401.22916-3-fchiby@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21soc: mediatek: add mtk-mmsys support for mt8195 vdosys0Jason-JH.Lin2-0/+381
1. Add mt8195 driver data with compatible "mediatek-mt8195-vdosys0". 2. Add mt8195 routing table settings of vdosys0. Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220927152704.12018-4-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0"Jason-JH.Lin3-517/+11
This reverts commit b804923b7ccb9c9629703364e927b48cd02a9254. Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys" to "mediatek,mt8195-vdosys0", we have to revert this patch and send a new patch with the new compatible. Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Link: https://lore.kernel.org/r/20220927152704.12018-3-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21Merge tag 'imx-drivers-6.2' of ↵Arnd Bergmann2-3/+11
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers i.MX drivers change for 6.2: - Improve imx8m-blk-ctrl driver to allow deferred probe in case that 'bus' genpd is not yet ready. - Add missing USB_1_PHY PD for i.MX scu-pd firmware driver. - Add GENPD_FLAG_ACTIVE_WAKEUP flag for i.MX8MM/N in GPCv2 driver, so that the power domain remains on if USB remote wakeup is enabled. * tag 'imx-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/n firmware: imx: scu-pd: add missed USB_1_PHY pd soc: imx: imx8m-blk-ctrl: Defer probe if 'bus' genpd is not yet ready Link: https://lore.kernel.org/r/20221119125733.32719-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'renesas-drivers-for-v6.2-tag2' of ↵Arnd Bergmann1-0/+22
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v6.2 (take two) - Add support for identifying the SoC revision on RZ/V2M. * tag 'renesas-drivers-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Identify RZ/V2M SoC Link: https://lore.kernel.org/r/cover.1668788925.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-17soc/tegra: cbb: Remove redundant dev_err callShang XiaoJing1-3/+1
devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_errLiu Shixin1-12/+1
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17soc: renesas: Identify RZ/V2M SoCPhil Edworthy1-0/+22
Add support for identifying the RZ/V2M (R9A09G011) SoC. Note that the SoC does not have a identification register. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> [biju: removed config changes ] Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221116102140.852889-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17genirq: Get rid of GENERIC_MSI_IRQ_DOMAINThomas Gleixner1-1/+1
Adjust to reality and remove another layer of pointless Kconfig indirection. CONFIG_GENERIC_MSI_IRQ is good enough to serve all purposes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20221111122014.524842979@linutronix.de
2022-11-14soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probeZhang Qilong1-0/+1
The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: 984aa6dbf4ca ("OMAP3: PM: Adding smartreflex driver support.") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221108080322.52268-3-zhangqilong3@huawei.com
2022-11-14soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probeZhang Qilong1-0/+1
The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: 41f93af900a2 ("soc: ti: add Keystone Navigator QMSS driver") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221108080322.52268-2-zhangqilong3@huawei.com
2022-11-14Merge tag 'renesas-arm-soc-for-v6.2-tag1' of ↵Arnd Bergmann1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc Renesas ARM SoC updates for v6.2 - Drop selecting GPIOLIB and PINCTRL, which are already automatically selected as part of the SOC_RENESAS config option in drivers/soc/renesas/Kconfig. * tag 'renesas-arm-soc-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: renesas: Drop selecting GPIOLIB and PINCTRL ARM: shmobile: Drop selecting GPIOLIB and PINCTRL soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS Link: https://lore.kernel.org/r/cover.1667558746.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14soc: loongson: add GUTS driver for loongson-2 platformsYinbo Zhu5-0/+218
The global utilities block controls PCIE device enabling, alternate function selection for multiplexed signals, consistency of HDA, USB and PCIE, configuration of memory controller, rtc controller, lio controller, and clock control. This patch adds a driver to manage and access global utilities block for LoongArch architecture Loongson-2 SoCs. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading firmware configuration by default, should eventually be added into this driver as well. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14Merge tag 'renesas-drivers-for-v6.2-tag1' of ↵Arnd Bergmann1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v6.2 - Let SOC_RENESAS select GPIOLIB and PINCTRL, so this does not have to be handled in two (soon three: arm/arm64/riscv), places. * tag 'renesas-drivers-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS Link: https://lore.kernel.org/r/cover.1667558747.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14soc: imx8m: Enable OCOTP clock before reading the registerXiaolei Wang1-0/+11
Commit 7d981405d0fd ("soc: imx8m: change to use platform driver") ever removed the dependency on bootloader for enabling OCOTP clock. It helped to fix a kexec kernel hang issue. But unfortunately it caused a regression on CAAM driver and got reverted. This is the second try to enable the OCOTP clock by directly calling clock API instead of indirectly enabling the clock via nvmem API. Fixes: ac34de14ac30 ("Revert "soc: imx8m: change to use platform driver"") Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-11soc/tegra: cbb: Check firewall before enabling error reportingSumit Gupta1-2/+81
To enable error reporting for a fabric to CCPLEX, we need to write its register for enabling error interrupt to CCPLEX during boot and later clear the error status register after error occurs. If a fabric's registers are protected and not accessible from CCPLEX, then accessing the registers will cause CBB firewall error. Add support to check whether write access from CCPLEX to the registers of a fabric is not blocked by it's firewall before enabling error reporting to CCPLEX for that fabric. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Add checks for potential out of bound errorsSumit Gupta1-2/+40
Added checks to avoid potential out of bounds errors which can happen if the 'slave map' and 'CBB errors' arrays are not correct or latest where some entries are missing. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Update slave maps for Tegra234Sumit Gupta1-21/+13
Updating the slave map for fabrics and using the same maps for DCE, RCE and SCE as they all are a replica in Tegra234. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194Sumit Gupta2-14/+13
In Tegra194 SoC, master_id bit range is different between cluster NOC and CBB NOC. Currently same bit range is used which results in wrong master_id value. Due to this, illegal accesses from the CCPLEX master do not result in a crash as expected. Fix this by using the correct range for the CBB NOC. Finally, it is only necessary to extract the master_id when the erd_mask_inband_err flag is set because when this is not set, a crash is always triggered. Fixes: b71344221466 ("soc/tegra: cbb: Add CBB 1.0 driver for Tegra194") Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: fuse: Use platform info with SoC revisionKartik2-2/+21
Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-09soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeupMaulik Shah3-1/+67
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
2022-11-09soc: qcom: rpmh-rsc: Save base address of drvMaulik Shah2-10/+10
Add changes to save drv's base address for rsc. This is used to read drv's configuration such as solver mode is supported or to write into CONTROL_TCS registers. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-6-ulf.hansson@linaro.org
2022-11-09soc: qcom: rpmh-rsc: Attach RSC to cluster PM domainLina Iyer2-5/+66
RSC is part the CPU subsystem and powers off the CPU domains when all the CPUs and no RPMH transactions are pending from any of the drivers. The RSC needs to flush the 'sleep' and 'wake' votes that are critical for saving power when all the CPUs are in idle. Let's make RSC part of the CPU PM domains, by attaching it to the cluster power domain. Registering for PM domain notifications, RSC driver can be notified that the last CPU is powering down. When the last CPU is powering down the domain, let's flush the 'sleep' and 'wake' votes that are stored in the data buffers into the hardware and also write next wakeup in CONTROL_TCS. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-3-ulf.hansson@linaro.org
2022-11-10soc/tegra: pmc: Process wake events during resumePetlozu Pravareshwar1-0/+41
During system resume, translate tier2 SC7 wake sources back into IRQs and do generic_handle_irq() to invoke the interrupt handlers for edge triggered wake events such as SW-wake. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Fix dual edge triggered wakesPetlozu Pravareshwar1-5/+176
When a wake event is defined to be triggered on both positive and negative edge of the input wake signal, it is crucial to know the current state of the signal when going into suspend. The intended way to obtain the current state of the wake signals is to read the WAKE_AOWAKE_SW_STATUS register, which should contains the raw state of the wake signals. However, this register is edge triggered, an edge will not be generated for signals that are already asserted prior to the assertion of WAKE_LATCH_SW. To workaround this, change the polarity of the wake level from '0' to '1' while latching the signals, as this will generate an edge for signals that are set to '1'. Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Add I/O pad table for Tegra234Petlozu Pravareshwar1-253/+403
Add I/O pad table for Tegra234 to allow configuring DPD mode and switching the pins to 1.8V or 3.3V as needed. On Tegra234, DPD registers are reorganized such that there is a DPD_REQ register and a DPD_STATUS register per pad group. Update the PMC driver accordingly. While at it, use the generated tables from tegra-pinmux-scripts to make the formatting of these tables more consistent. Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> [treding@nvidia.com: generate tables from tegra-pinmux-scripts] Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-09soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()Yang Yingliang1-4/+11
The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-09soc: sifive: ccache: fix missing free_irq() in error path in ↵Yang Yingliang1-1/+4
sifive_ccache_init() Add missing free_irq() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-09soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()Yang Yingliang1-4/+11
Add missing iounmap() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-08ARM: ux500: do not directly dereference __iomemJason A. Donenfeld1-6/+4
Sparse reports that calling add_device_randomness() on `uid` is a violation of address spaces. And indeed the next usage uses readl() properly, but that was left out when passing it toadd_device_ randomness(). So instead copy the whole thing to the stack first. Fixes: 4040d10a3d44 ("ARM: ux500: add DB serial number to entropy pool") Cc: Linus Walleij <linus.walleij@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/202210230819.loF90KDh-lkp@intel.com/ Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20221108123755.207438-1-Jason@zx2c4.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-08ARM: 9263/1: use .arch directives instead of assembler command line flagsNick Desaulniers2-1/+1
Similar to commit a6c30873ee4a ("ARM: 8989/1: use .fpu assembler directives instead of assembler arguments"). GCC and GNU binutils support setting the "sub arch" via -march=, -Wa,-march, target function attribute, and .arch assembler directive. Clang was missing support for -Wa,-march=, but this was implemented in clang-13. The behavior of both GCC and Clang is to prefer -Wa,-march= over -march= for assembler and assembler-with-cpp sources, but Clang will warn about the -march= being unused. clang: warning: argument unused during compilation: '-march=armv6k' [-Wunused-command-line-argument] Since most assembler is non-conditionally assembled with one sub arch (modulo arch/arm/delay-loop.S which conditionally is assembled as armv4 based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the .arch assembler directive. Add a few more instances found in compile testing as found by Arnd and Nathan. Link: https://github.com/llvm/llvm-project/commit/1d51c699b9e2ebc5bcfdbe85c74cc871426333d4 Link: https://bugs.llvm.org/show_bug.cgi?id=48894 Link: https://github.com/ClangBuiltLinux/linux/issues/1195 Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-11-08soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config funcXinlei Lee2-9/+26
The difference between MT8186 and other ICs is that when modifying the output format, we need to modify the mmsys_base+0x400 register to take effect. So when setting the dpi output format, we need to call mtk_mmsys_ddp_dpi_fmt_config to set it to MT8186 synchronously. Commit a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for MT8186") lacked some of the possible output formats and also had a wrong bitmask. Add the missing output formats and fix the bitmask. While at it, also update mtk_mmsys_ddp_dpi_fmt_config() to use generic formats, so that it is slightly easier to extend for other platforms. Fixes: a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for MT8186") Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-07soc: qcom: apr: Add check for idr_alloc and of_property_read_string_indexJiasheng Jiang1-3/+12
As idr_alloc() and of_property_read_string_index() can return negative numbers, it should be better to check the return value and deal with the exception. Therefore, it should be better to use goto statement to stop and return error. Fixes: 6adba21eb434 ("soc: qcom: Add APR bus driver") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107014403.3606-1-jiasheng@iscas.ac.cn
2022-11-07soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id tableMelody Olvera1-0/+6
Add SoC ID table entries for the QDU1000 and QRU1000 platforms and their variants. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-6-quic_molvera@quicinc.com
2022-11-07soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domainsMelody Olvera1-0/+14
Add the power domains exposed by RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-4-quic_molvera@quicinc.com
2022-11-05soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PMAngeloGioacchino Del Regno1-0/+33
Implement the support for SAW v2.3, used in at least MSM8976, MSM8956 and APQ variants and while at it also add the configuration for the MSM8976's little (a53) and big (a72) clusters cache power management. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Marijn: reorder struct definitions to follow high-to-low order] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104133452.131227-3-angelogioacchino.delregno@collabora.com
2022-11-05soc: qcom: llcc: make irq truly optionalLuca Weiss1-1/+1
The function platform_get_irq prints an error message into the kernel log when the irq isn't found. Since the interrupt is actually optional and not provided by some SoCs, use platform_get_irq_optional which does not print an error message. Fixes: c081f3060fab ("soc: qcom: Add support to register LLCC EDAC driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104153041.412020-1-luca.weiss@fairphone.com
2022-11-05soc: qcom: spm: Add MSM8939 SPM register dataVincent Knecht1-0/+13
Add SPM register information and initialization values for QCOM MSM8939 SoC. Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221019171004.1080911-2-vincent.knecht@mailoo.org
2022-11-03soc: ti: k3-ringacc: Allow the driver to be built as modulePeter Ujfalusi2-3/+27
The ring accelerator driver can be built as module since all depending functions are exported. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Nicolas Frayer <nfrayer@baylibre.com> Reviewed-by: Nicolas Frayer <nfrayer@baylibre.com> Link: https://lore.kernel.org/r/20221029075356.7296-1-peter.ujfalusi@gmail.com
2022-11-02soc: fsl: qe: Switch to use fwnode instead of of_nodeAndy Shevchenko1-1/+3
The OF node in the GPIO library is deprecated and soon will be removed. GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-11-01soc: fsl: qe: Avoid using gpio_to_desc()Linus Walleij1-36/+30
The qe gpio driver is a custom API combined GPIO and pin control driver that exist outside of the pin control subsystem for historical reasons. We want to get rid of the old GPIO numberspace, so instead of calling gpio_to_desc() we get the gpio descriptor for the requested line from the device tree directly without passing through the GPIO numberspace, and then we get the gpiochip from the descriptor. Using the reference counting inside the gpio descriptor we can drop the reference counting code in this driver. A second gpiod_get() will not succeed. To obtain the local hardware offset of the GPIO line, the driver need to include the header from the gpiolib internals. This isn't pretty but it is the lesser evil compared to keeping the code as a roadblock to gpiolib refactoring. A proper solution would be to rewrite the driver as a real pin control driver with a built-in gpio_chip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20221027081108.174662-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-10-29soc: imx: imx93-pd: Fix the error handling path of imx93_pd_probe()Christophe JAILLET1-2/+15
In imx93_pd_probe(); if an error occurs, some resources need to be released as done in the remove function. Fixes: 0a0f7cc25d4a ("soc: imx: add i.MX93 SRC power domain driver") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-10-29soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/nLi Jun1-0/+3
To keep the power domain on if usb remote wakeup is enabled, add the GENPD_FLAG_ACTIVE_WAKEUP for otg1/2 of imx8mm/n. Signed-off-by: Li Jun <jun.li@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-10-28drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as staticChen Jiahao1-1/+1
There is a sparse warning shown below: drivers/soc/ti/knav_qmss_queue.c:70:12: warning: symbol 'knav_acc_firmwares' was not declared. Should it be static? Since 'knav_acc_firmwares' is only called within knav_qmss_queue.c, mark it as static to fix the warning. Fixes: 96ee19becc3b ("soc: ti: add firmware file name as part of the driver") Signed-off-by: Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221019153212.72350-1-chenjiahao16@huawei.com
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-26 13:24:08 +0000