~sima/drm - danvet's drm/ playground

Age	Commit message (Expand)	Author	Files	Lines
2015-10-23	fpga: zynq-fpga: Fix issue with drvdata being overwritten.	Moritz Fischer	1	-3/+4
2015-10-23	fpga: zynq-fpga: Change fw format to handle bin instead of bit.	Moritz Fischer	1	-22/+2
2015-10-23	fpga: zynq-fpga: Fix unbalanced clock handling	Moritz Fischer	1	-2/+2
2015-10-17	fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000	Moritz Fischer	1	-0/+533