~sima/drm - danvet's drm/ playground

Age	Commit message (Expand)	Author	Files	Lines
2019-02-18	clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static	Wei Yongjun	1	-1/+1
2019-02-15	Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Arnd Bergmann	1	-16/+504
2019-02-06	clk: tegra: dfll: add CVB tables for Tegra210	Joseph Lo	1	-0/+426
2019-02-06	clk: tegra: dfll: CVB calculation alignment with the regulator	Joseph Lo	1	-5/+44
2019-02-06	clk: tegra: dfll: registration for multiple SoCs	Peter De Schrijver	1	-11/+34
2019-01-09	clk: tegra: dfll: Fix a potential Oop in remove()	Dan Carpenter	1	-1/+3
2017-11-01	clk: tegra: dfll: Fix drvdata overwriting issue	Nicolin Chen	1	-7/+5
2016-11-10	clk: tegra: dfll: Use builtin_platform_driver to simplify the code	Wei Yongjun	1	-6/+1
2016-11-04	clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular	Paul Gortmaker	1	-14/+2
2016-04-28	clk: tegra: dfll: Reformat CVB frequency table	Thierry Reding	1	-25/+25
2016-04-28	clk: tegra: dfll: Properly clean up on failure and removal	Thierry Reding	1	-4/+27
2016-04-28	clk: tegra: dfll: Make code more comprehensible	Thierry Reding	1	-6/+5
2016-04-28	clk: tegra: dfll: Reference CVB table instead of copying data	Thierry Reding	1	-14/+9
2015-07-16	clk: tegra: Add Tegra124 DFLL clocksource platform driver	Tuomas Tynkkynen	1	-0/+166