| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-09-04 | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | Lad Prabhakar | 1 | -1/+1 |
| 2018-09-28 | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 1 | -4/+1 |
| 2018-04-16 | clk: renesas: r8a7792: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-02-20 | clk: renesas: r8a7792: Add rwdt clock | Geert Uytterhoeven | 1 | -0/+2 |
| 2017-07-17 | clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks | Geert Uytterhoeven | 1 | -0/+7 |
| 2017-05-24 | clk: renesas: r8a7792: Add new CPG/MSSR driver | Geert Uytterhoeven | 1 | -0/+221 |
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index : ~sima/drm | |
| danvet's drm/ playground | danvet |
| summaryrefslogtreecommitdiff |