| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2023-07-19 | clk: Explicitly include correct DT includes | Rob Herring | 1 | -3/+0 |
| 2019-10-28 | clk: hi6220: use CLK_OF_DECLARE_DRIVER | Peter Griffin | 1 | -1/+2 |
| 2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner | 1 | -4/+1 |
| 2017-11-01 | clk: hi6220: mark clock cs_atb_syspll as critical | Leo Yan | 1 | -1/+1 |
| 2017-08-31 | clk: hi6220: change watchdog clock source | Leo Yan | 1 | -3/+3 |
| 2017-06-19 | clk: hi6220: add acpu clock | Zhangfei Gao | 1 | -0/+22 |
| 2017-04-12 | clk: hi6220: add debug APB clock | Leo Yan | 1 | -0/+1 |
| 2016-10-17 | clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init | Shawn Guo | 1 | -2/+2 |
| 2016-07-06 | clk: hi6220: Change syspll and media_syspll clk to 1.19GHz | Xinliang Liu | 1 | -2/+2 |
| 2016-06-30 | clk: hi6220: Add RTC clock for pl031 | Zhangfei Gao | 1 | -0/+2 |
| 2016-03-02 | clk: hisilicon: Remove CLK_IS_ROOT | Stephen Boyd | 1 | -13/+13 |
| 2015-06-03 | clk: hi6220: Clock driver support for Hisilicon hi6220 SoC | Bintian Wang | 1 | -0/+284 |
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index : ~sima/drm | |
| danvet's drm/ playground | danvet |
| summaryrefslogtreecommitdiff |