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authorMarian Postevca <posteuca@mutex.one>2023-08-30 01:01:14 +0300
committerMark Brown <broonie@kernel.org>2023-09-11 01:24:09 +0100
commit869f30782cdad0a86598a700a864e4a2bf44f8cc (patch)
treee6d739d3988fc88a1644fee88ffbb9dd98b5ebea /sound/soc/codecs/es8316.h
parenta43c0dc1004cbe2edbae9b6e6793db71f6896449 (diff)
ASoC: es8316: Enable support for MCLK div by 2
To properly support a line of Huawei laptops with an AMD CPU and an ES8336 codec connected to the ACP3X module, we need to enable the codec option to divide the MCLK by 2. This is needed because for at least one SKU that has a 48Mhz MCLK the sound is distorted unless the MCLK div by 2 option is enabled. The option to divide the MCLK will first be tried. If no suitable clocking can be generated from this frequency, then the normal non-halved MCLK frequency will be tried. Signed-off-by: Marian Postevca <posteuca@mutex.one> Link: https://lore.kernel.org/r/20230829220116.1159-4-posteuca@mutex.one Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/es8316.h')
-rw-r--r--sound/soc/codecs/es8316.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/sound/soc/codecs/es8316.h b/sound/soc/codecs/es8316.h
index c335138e2837..0ff16f948690 100644
--- a/sound/soc/codecs/es8316.h
+++ b/sound/soc/codecs/es8316.h
@@ -129,4 +129,7 @@
#define ES8316_GPIO_FLAG_GM_NOT_SHORTED 0x02
#define ES8316_GPIO_FLAG_HP_NOT_INSERTED 0x04
+/* ES8316_CLKMGR_CLKSW */
+#define ES8316_CLKMGR_CLKSW_MCLK_DIV 0x80
+
#endif