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authorDinh Nguyen <dinguyen@opensource.altera.com>2013-11-20 09:39:17 -0600
committerDinh Nguyen <dinguyen@opensource.altera.com>2015-07-22 13:16:51 -0500
commitc5dab6e2c1f7bbf33ec855cebae92a1566ed6d04 (patch)
treedbd69f64bd7bc2dee0495ca914424ec04b791d1c /sound/oss
parent57c0f8c9c45365d167f8606dad7fde9565432b7a (diff)
ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
The l3_sp_clk's parent should be the l3_mp_clk. This will account for the extra divider that is present for the l3_mp_clk. The dbg_clk's parent should be the dbg_at_clk. This will account for the extra divider that is present for the dbg_at_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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