diff options
| author | Oswald Buddenhagen <oswald.buddenhagen@gmx.de> | 2023-06-12 21:13:19 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2023-06-13 07:41:07 +0200 |
| commit | e73b597e63ebad26d9dee5feb5d47251ed53b8a4 (patch) | |
| tree | 2d966bcf9b1e5d2317dcb4396383fd7cc0ba62e5 /include/sound | |
| parent | 60985241bfc61c6d6d85a78e0f29c866c546c7f5 (diff) | |
ALSA: emu10k1: query rate of external clock sources on E-MU cards
The value isn't used yet; the subsequent commits will do that.
This ignores the existence of rates above 48 kHz, which is fine, as the
hardware will just switch to the fallback clock source when fed with a
rate which is incompatible with the base clock multiplier, which
currently is always x1.
The sample rate display in /proc spdif-in is adjusted to reflect our
understanding of the input rates.
This is tested only with an 0404b card without sync card, so there is a
lot of room for improvement.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-4-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'include/sound')
| -rw-r--r-- | include/sound/emu10k1.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index 703ef441bb2a..d64cf1697586 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -1110,6 +1110,9 @@ SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ +// The actual code disagrees about the bit width of the registers - +// the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1) + #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */ @@ -1669,6 +1672,7 @@ struct snd_emu1010 { unsigned int adc_pads; /* bit mask */ unsigned int dac_pads; /* bit mask */ unsigned int wclock; /* Cached register value */ + unsigned int word_clock; /* Cached effective value */ unsigned int clock_source; unsigned int clock_fallback; unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ @@ -1825,6 +1829,7 @@ void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst); +int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src); void snd_emu1010_update_clock(struct snd_emu10k1 *emu); unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); |