diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-04-07 16:52:40 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-04-07 16:52:40 +0200 |
| commit | fbb0ad422960cc2199c31d33f1095a39dfee5cfa (patch) | |
| tree | 4134a17f038eff33e0d9106115d9ace73e005598 /drivers | |
| parent | 39b53e23532f5da13757d88eeb1290da864bfdf4 (diff) | |
| parent | cbc336c09b6d6dfb24d20c955599123308fa2fe2 (diff) | |
Merge tag 'phy-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes:
phy-for-5.13
- Updates:
- Yaml conversion for mvebu-utmi binding, bcm-ns-usb2 and
bcm-ns-usb3 bindings
- Mediatek dsi and hdmi phy updates
- TI j721e-wiz updates for AM64
- Cadence-torrent phy updates for SGMII/QSGMII
- New support:
- usb3-dp phy for Qualcomm SM8250
- UTMI phy for Armada CP110
- USB phy for Qualcomm SC7280
- Binding and driver for Sparx5 ethernet serdes
* tag 'phy-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (75 commits)
phy: fix resource_size.cocci warnings
phy: Sparx5 Eth SerDes: Use direct register operations
phy: hisilicon: Use the correct HiSilicon copyright
phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMON
phy: qcom-qmp: add support for sm8250-usb3-dp phy
phy: qcom-qmp: rename common registers
phy: qcom-qmp: move DP functions to callbacks
dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SM8250
dt-bindings: phy: qcom,qmp-usb3-dp-phy: move usb3 compatibles back to qcom,qmp-phy.yaml
phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMII
dt-bindings: phy: fix dt_binding_check warning in mediatek, ufs-phy.yaml
phy: zynqmp: Handle the clock enable/disable properly
dt-bindings: phy: bcm-ns-usb3-phy: convert to yaml
dt-bindings: phy: bcm-ns-usb2-phy: convert to yaml
phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5
phy: cadence-torrent: Add delay for PIPE clock to be stable
phy: cadence-torrent: Explicitly request exclusive reset control
phy: cadence-torrent: Do not configure SERDES if it's already configured
phy: cadence-torrent: Group reset APIs and clock APIs
phy: ti: j721e-wiz: Do not configure wiz if its already configured
...
Diffstat (limited to 'drivers')
30 files changed, 7610 insertions, 307 deletions
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 68d9c2f6a5ca..54c1f2f0985f 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -71,6 +71,7 @@ source "drivers/phy/ingenic/Kconfig" source "drivers/phy/lantiq/Kconfig" source "drivers/phy/marvell/Kconfig" source "drivers/phy/mediatek/Kconfig" +source "drivers/phy/microchip/Kconfig" source "drivers/phy/motorola/Kconfig" source "drivers/phy/mscc/Kconfig" source "drivers/phy/qualcomm/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 32261e164abd..adac1b1a39d1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -20,6 +20,7 @@ obj-y += allwinner/ \ lantiq/ \ marvell/ \ mediatek/ \ + microchip/ \ motorola/ \ mscc/ \ qualcomm/ \ diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 09256339bd04..fd92b73b7109 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -94,7 +94,7 @@ config PHY_BRCM_USB depends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST depends on OF select GENERIC_PHY - select SOC_BRCMSTB + select SOC_BRCMSTB if ARCH_BRCMSTB default ARCH_BCM4908 default ARCH_BRCMSTB help diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 432832bdbd16..a62910ff5591 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -7,6 +7,7 @@ config PHY_CADENCE_TORRENT tristate "Cadence Torrent PHY driver" depends on OF depends on HAS_IOMEM + depends on COMMON_CLK select GENERIC_PHY help Support for Cadence Torrent PHY. @@ -24,6 +25,7 @@ config PHY_CADENCE_DPHY config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on OF && HAS_IOMEM && RESET_CONTROLLER + depends on COMMON_CLK select GENERIC_PHY help Enable this to support the Cadence Sierra PHY driver diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 26a0badabe38..5c68e31c5939 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -7,6 +7,7 @@ * */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> @@ -20,10 +21,12 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-cadence.h> /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET 0x0 #define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A @@ -31,6 +34,9 @@ #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 +#define SIERRA_CMN_REFRCV_PREG 0x98 +#define SIERRA_CMN_REFRCV1_PREG 0xB8 +#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -144,6 +150,19 @@ #define SIERRA_MAX_LANES 16 #define PLL_LOCK_TIME 100000 +#define CDNS_SIERRA_OUTPUT_CLOCKS 2 +#define CDNS_SIERRA_INPUT_CLOCKS 5 +enum cdns_sierra_clock_input { + PHY_CLK, + CMN_REFCLK_DIG_DIV, + CMN_REFCLK1_DIG_DIV, + PLL0_REFCLK, + PLL1_REFCLK, +}; + +#define SIERRA_NUM_CMN_PLLC 2 +#define SIERRA_NUM_CMN_PLLC_PARENTS 2 + static const struct reg_field macro_id_type = REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); static const struct reg_field phy_pll_cfg_1 = @@ -151,6 +170,53 @@ static const struct reg_field phy_pll_cfg_1 = static const struct reg_field pllctrl_lock = REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); +static const char * const clk_names[] = { + [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", + [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", +}; + +enum cdns_sierra_cmn_plllc { + CMN_PLLLC, + CMN_PLLLC1, +}; + +struct cdns_sierra_pll_mux_reg_fields { + struct reg_field pfdclk_sel_preg; + struct reg_field plllc1en_field; + struct reg_field termen_field; +}; + +static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { + [CMN_PLLLC] = { + .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), + .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), + .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), + }, + [CMN_PLLLC1] = { + .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), + .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), + .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), + }, +}; + +struct cdns_sierra_pll_mux { + struct clk_hw hw; + struct regmap_field *pfdclk_sel_preg; + struct regmap_field *plllc1en_field; + struct regmap_field *termen_field; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_pll_mux(_hw) \ + container_of(_hw, struct cdns_sierra_pll_mux, hw) + +static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = { + [CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK }, + [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK }, +}; + +static u32 cdns_sierra_pll_mux_table[] = { 0, 1 }; + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -197,12 +263,15 @@ struct cdns_sierra_phy { struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; - struct clk *clk; - struct clk *cmn_refclk_dig_div; - struct clk *cmn_refclk1_dig_div; + struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; + struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; + struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; + struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; int nsubnodes; u32 num_lanes; bool autoconf; + struct clk_onecell_data clk_data; + struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS]; }; static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) @@ -281,8 +350,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) if (phy->autoconf) return 0; - clk_set_rate(phy->cmn_refclk_dig_div, 25000000); - clk_set_rate(phy->cmn_refclk1_dig_div, 25000000); + clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); + clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); if (ins->phy_type == PHY_TYPE_PCIE) { num_cmn_regs = phy->init_data->pcie_cmn_regs; num_ln_regs = phy->init_data->pcie_ln_regs; @@ -319,6 +388,12 @@ static int cdns_sierra_phy_on(struct phy *gphy) u32 val; int ret; + ret = reset_control_deassert(sp->phy_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY out of reset\n"); + return ret; + } + /* Take the PHY lane group out of reset */ ret = reset_control_deassert(ins->lnk_rst); if (ret) { @@ -358,6 +433,153 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table, 0, val); +} + +static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *plllc1en_field = mux->plllc1en_field; + struct regmap_field *termen_field = mux->termen_field; + struct regmap_field *field = mux->pfdclk_sel_preg; + int val, ret; + + ret = regmap_field_write(plllc1en_field, 0); + ret |= regmap_field_write(termen_field, 0); + if (index == 1) { + ret |= regmap_field_write(plllc1en_field, 1); + ret |= regmap_field_write(termen_field, 1); + } + + val = cdns_sierra_pll_mux_table[index]; + ret |= regmap_field_write(field, val); + + return ret; +} + +static const struct clk_ops cdns_sierra_pll_mux_ops = { + .set_parent = cdns_sierra_pll_mux_set_parent, + .get_parent = cdns_sierra_pll_mux_get_parent, +}; + +static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, + struct regmap_field *pfdclk1_sel_field, + struct regmap_field *plllc1en_field, + struct regmap_field *termen_field, + int clk_index) +{ + struct cdns_sierra_pll_mux *mux; + struct device *dev = sp->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + char clk_name[100]; + struct clk *clk; + int i; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + for (i = 0; i < num_parents; i++) { + clk = sp->input_clks[pll_mux_parent_index[clk_index][i]]; + if (IS_ERR_OR_NULL(clk)) { + dev_err(dev, "No parent clock for derived_refclk\n"); + return PTR_ERR(clk); + } + parent_names[i] = __clk_get_name(clk); + } + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]); + + init = &mux->clk_data; + + init->ops = &cdns_sierra_pll_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->pfdclk_sel_preg = pfdclk1_sel_field; + mux->plllc1en_field = plllc1en_field; + mux->termen_field = termen_field; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + sp->output_clks[clk_index] = clk; + + return 0; +} + +static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) +{ + struct regmap_field *pfdclk1_sel_field; + struct regmap_field *plllc1en_field; + struct regmap_field *termen_field; + struct device *dev = sp->dev; + int ret = 0, i, clk_index; + + clk_index = CDNS_SIERRA_PLL_CMNLC; + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { + pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; + plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; + termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; + + ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field, + termen_field, clk_index); + if (ret) { + dev_err(dev, "Fail to register cmn plllc mux\n"); + return ret; + } + } + + return 0; +} + +static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) +{ + struct device *dev = sp->dev; + struct device_node *node = dev->of_node; + + of_clk_del_provider(node); +} + +static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) +{ + struct device *dev = sp->dev; + struct device_node *node = dev->of_node; + int ret; + + ret = cdns_sierra_phy_register_pll_mux(sp); + if (ret) { + dev_err(dev, "Failed to pll mux clocks\n"); + return ret; + } + + sp->clk_data.clks = sp->output_clks; + sp->clk_data.clk_num = CDNS_SIERRA_OUTPUT_CLOCKS; + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &sp->clk_data); + if (ret) + dev_err(dev, "Failed to add clock provider: %s\n", node->name); + + return ret; +} + static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { @@ -396,6 +618,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) { struct device *dev = sp->dev; struct regmap_field *field; + struct reg_field reg_field; struct regmap *regmap; int i; @@ -407,6 +630,32 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) } sp->macro_id_type = field; + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); + return PTR_ERR(field); + } + sp->cmn_plllc_pfdclk1_sel_preg[i] = field; + + reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; + + reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_termen_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -471,6 +720,110 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get_optional(dev, "phy_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clock phy_clk\n"); + return PTR_ERR(clk); + } + sp->input_clks[PHY_CLK] = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; + + clk = devm_clk_get_optional(dev, "pll0_refclk"); + if (IS_ERR(clk)) { + dev_err(dev, "pll0_refclk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->input_clks[PLL0_REFCLK] = clk; + + clk = devm_clk_get_optional(dev, "pll1_refclk"); + if (IS_ERR(clk)) { + dev_err(dev, "pll1_refclk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->input_clks[PLL1_REFCLK] = clk; + + return 0; +} + +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc1: + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + +err_pll_cmnlc: + clk_disable_unprepare(sp->input_clks[PHY_CLK]); + + return ret; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + clk_disable_unprepare(sp->input_clks[PHY_CLK]); +} + +static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct reset_control *rst; + + rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get reset\n"); + return PTR_ERR(rst); + } + sp->phy_rst = rst; + + rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get apb reset\n"); + return PTR_ERR(rst); + } + sp->apb_rst = rst; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -481,7 +834,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) unsigned int id_value; int i, ret, node = 0; void __iomem *base; - struct clk *clk; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) @@ -518,43 +870,21 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get_optional(dev, "phy_clk"); - if (IS_ERR(sp->clk)) { - dev_err(dev, "failed to get clock phy_clk\n"); - return PTR_ERR(sp->clk); - } - - sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); - if (IS_ERR(sp->phy_rst)) { - dev_err(dev, "failed to get reset\n"); - return PTR_ERR(sp->phy_rst); - } - - sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); - if (IS_ERR(sp->apb_rst)) { - dev_err(dev, "failed to get apb reset\n"); - return PTR_ERR(sp->apb_rst); - } - - clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk_dig_div clock not found\n"); - ret = PTR_ERR(clk); + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) return ret; - } - sp->cmn_refclk_dig_div = clk; - clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); - ret = PTR_ERR(clk); + ret = cdns_sierra_clk_register(sp); + if (ret) return ret; - } - sp->cmn_refclk1_dig_div = clk; - ret = clk_prepare_enable(sp->clk); + ret = cdns_sierra_phy_get_resets(sp, dev); if (ret) - return ret; + goto unregister_clk; + + ret = cdns_sierra_phy_enable_clocks(sp); + if (ret) + goto unregister_clk; /* Enable APB */ reset_control_deassert(sp->apb_rst); @@ -571,6 +901,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dn, child) { struct phy *gphy; + if (!(of_node_name_eq(child, "phy") || + of_node_name_eq(child, "link"))) + continue; + sp->phys[node].lnk_rst = of_reset_control_array_get_exclusive(child); @@ -616,7 +950,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - reset_control_deassert(sp->phy_rst); return PTR_ERR_OR_ZERO(phy_provider); put_child: @@ -626,8 +959,10 @@ put_child2: reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->clk); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); +unregister_clk: + cdns_sierra_clk_unregister(sp); return ret; } @@ -640,6 +975,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. @@ -648,6 +984,9 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->phys[i].lnk_rst); reset_control_put(phy->phys[i].lnk_rst); } + + cdns_sierra_clk_unregister(phy); + return 0; } diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 591a15834b48..0477e7beebbf 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -7,7 +7,9 @@ */ #include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-cadence.h> #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> @@ -84,6 +86,8 @@ #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U +#define CMN_CDIAG_REFCLK_OVRD 0x004CU +#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U #define CMN_BGCAL_INIT_TMR 0x0064U #define CMN_BGCAL_ITER_TMR 0x0065U #define CMN_IBCAL_INIT_TMR 0x0074U @@ -122,6 +126,8 @@ #define CMN_PLL1_FRACDIVH_M0 0x00D2U #define CMN_PLL1_HIGH_THR_M0 0x00D3U #define CMN_PLL1_DSM_DIAG_M0 0x00D4U +#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U +#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U #define CMN_PLL1_SS_CTRL1_M0 0x00D8U #define CMN_PLL1_SS_CTRL2_M0 0x00D9U #define CMN_PLL1_SS_CTRL3_M0 0x00DAU @@ -163,10 +169,12 @@ #define TX_TXCC_CPOST_MULT_00 0x004CU #define TX_TXCC_CPOST_MULT_01 0x004DU #define TX_TXCC_MGNFS_MULT_000 0x0050U +#define TX_TXCC_MGNFS_MULT_100 0x0054U #define DRV_DIAG_TX_DRV 0x00C6U #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U #define XCVR_DIAG_HSCLK_SEL 0x00E6U #define XCVR_DIAG_HSCLK_DIV 0x00E7U +#define XCVR_DIAG_RXCLK_CTRL 0x00E9U #define XCVR_DIAG_BIDI_CTRL 0x00EAU #define XCVR_DIAG_PSC_OVRD 0x00EBU #define TX_PSC_A0 0x0100U @@ -206,6 +214,7 @@ #define RX_DIAG_ACYA 0x01FFU /* PHY PCS common registers */ +#define PHY_PIPE_CMN_CTRL1 0x0000U #define PHY_PLL_CFG 0x000EU #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U @@ -216,6 +225,10 @@ #define PHY_PMA_CMN_CTRL2 0x0001U #define PHY_PMA_PLL_RAW_CTRL 0x0003U +static const char * const clk_names[] = { + [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", +}; + static const struct reg_field phy_pll_cfg = REG_FIELD(PHY_PLL_CFG, 0, 1); @@ -231,6 +244,26 @@ static const struct reg_field phy_pma_pll_raw_ctrl = static const struct reg_field phy_reset_ctrl = REG_FIELD(PHY_RESET, 8, 8); +static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0); + +#define REFCLK_OUT_NUM_CMN_CONFIG 5 + +enum cdns_torrent_refclk_out_cmn { + CMN_CDIAG_REFCLK_OVRD_4, + CMN_CDIAG_REFCLK_DRV0_CTRL_1, + CMN_CDIAG_REFCLK_DRV0_CTRL_4, + CMN_CDIAG_REFCLK_DRV0_CTRL_5, + CMN_CDIAG_REFCLK_DRV0_CTRL_6, +}; + +static const struct reg_field refclk_out_cmn_cfg[] = { + [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4), + [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), + [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), + [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), + [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), +}; + enum cdns_torrent_phy_type { TYPE_NONE, TYPE_DP, @@ -279,6 +312,8 @@ struct cdns_torrent_phy { struct regmap_field *phy_pma_cmn_ctrl_2; struct regmap_field *phy_pma_pll_raw_ctrl; struct regmap_field *phy_reset_ctrl; + struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1]; + struct clk_onecell_data clk_data; }; enum phy_powerstate { @@ -288,6 +323,16 @@ enum phy_powerstate { POWERSTATE_A3 = 3, }; +struct cdns_torrent_derived_refclk { + struct clk_hw hw; + struct regmap_field *phy_pipe_cmn_ctrl1_0; + struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG]; + struct clk_init_data clk_data; +}; + +#define to_cdns_torrent_derived_refclk(_hw) \ + container_of(_hw, struct cdns_torrent_derived_refclk, hw) + static int cdns_torrent_phy_init(struct phy *phy); static int cdns_torrent_dp_init(struct phy *phy); static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, @@ -326,6 +371,19 @@ static const struct phy_ops cdns_torrent_phy_ops = { .owner = THIS_MODULE, }; +static int cdns_torrent_noop_phy_on(struct phy *phy) +{ + /* Give 5ms to 10ms delay for the PIPE clock to be stable */ + usleep_range(5000, 10000); + + return 0; +} + +static const struct phy_ops noop_ops = { + .power_on = cdns_torrent_noop_phy_on, + .owner = THIS_MODULE, +}; + struct cdns_reg_pairs { u32 val; u32 off; @@ -1604,6 +1662,108 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) return ret; } +static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) +{ + struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); + + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1); + regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1); + + return 0; +} + +static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) +{ + struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); + + regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0); +} + +static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) +{ + struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); + int val; + + regmap_field_read(derived_refclk->phy_pipe_cmn_ctrl1_0, &val); + + return !!val; +} + +static const struct clk_ops cdns_torrent_derived_refclk_ops = { + .enable = cdns_torrent_derived_refclk_enable, + .disable = cdns_torrent_derived_refclk_disable, + .is_enabled = cdns_torrent_derived_refclk_is_enabled, +}; + +static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) +{ + struct cdns_torrent_derived_refclk *derived_refclk; + struct device *dev = cdns_phy->dev; + struct regmap_field *field; + struct clk_init_data *init; + const char *parent_name; + struct regmap *regmap; + char clk_name[100]; + struct clk *clk; + int i; + + derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); + if (!derived_refclk) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + clk_names[CDNS_TORRENT_REFCLK_DRIVER]); + + clk = devm_clk_get_optional(dev, "phy_en_refclk"); + if (IS_ERR(clk)) { + dev_err(dev, "No parent clock for derived_refclk\n"); + return PTR_ERR(clk); + } + + init = &derived_refclk->clk_data; + + if (clk) { + parent_name = __clk_get_name(clk); + init->parent_names = &parent_name; + init->num_parents = 1; + } + init->ops = &cdns_torrent_derived_refclk_ops; + init->flags = 0; + init->name = clk_name; + + regmap = cdns_phy->regmap_phy_pcs_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0); + if (IS_ERR(field)) { + dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n"); + return PTR_ERR(field); + } + derived_refclk->phy_pipe_cmn_ctrl1_0 = field; + + regmap = cdns_phy->regmap_common_cdb; + for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) { + field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); + if (IS_ERR(field)) { + dev_err(dev, "CMN reg field init failed\n"); + return PTR_ERR(field); + } + derived_refclk->cmn_fields[i] = field; + } + + derived_refclk->hw.init = init; + + clk = devm_clk_register(dev, &derived_refclk->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + cdns_phy->clks[CDNS_TORRENT_REFCLK_DRIVER] = clk; + + return 0; +} + static int cdns_torrent_phy_on(struct phy *phy) { struct cdns_torrent_inst *inst = phy_get_drvdata(phy); @@ -2071,6 +2231,85 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) return 0; } +static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) +{ + struct device *dev = cdns_phy->dev; + + of_clk_del_provider(dev->of_node); +} + +static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) +{ + struct device *dev = cdns_phy->dev; + struct device_node *node = dev->of_node; + int ret; + + ret = cdns_torrent_derived_refclk_register(cdns_phy); + if (ret) { + dev_err(dev, "failed to register derived refclk\n"); + return ret; + } + + cdns_phy->clk_data.clks = cdns_phy->clks; + cdns_phy->clk_data.clk_num = CDNS_TORRENT_REFCLK_DRIVER + 1; + + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &cdns_phy->clk_data); + if (ret) { + dev_err(dev, "Failed to add clock provider: %s\n", node->name); + return ret; + } + + return 0; +} + +static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy) +{ + struct device *dev = cdns_phy->dev; + + cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); + if (IS_ERR(cdns_phy->phy_rst)) { + dev_err(dev, "%s: failed to get reset\n", + dev->of_node->full_name); + return PTR_ERR(cdns_phy->phy_rst); + } + + cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb"); + if (IS_ERR(cdns_phy->apb_rst)) { + dev_err(dev, "%s: failed to get apb reset\n", + dev->of_node->full_name); + return PTR_ERR(cdns_phy->apb_rst); + } + + return 0; +} + +static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) +{ + struct device *dev = cdns_phy->dev; + int ret; + + cdns_phy->clk = devm_clk_get(dev, "refclk"); + if (IS_ERR(cdns_phy->clk)) { + dev_err(dev, "phy ref clock not found\n"); + return PTR_ERR(cdns_phy->clk); + } + + ret = clk_prepare_enable(cdns_phy->clk); + if (ret) { + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); + return ret; + } + + cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); + if (!(cdns_phy->ref_clk_rate)) { + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); + clk_disable_unprepare(cdns_phy->clk); + return -EINVAL; + } + + return 0; +} + static int cdns_torrent_phy_probe(struct platform_device *pdev) { struct cdns_torrent_phy *cdns_phy; @@ -2080,6 +2319,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) struct device_node *child; int ret, subnodes, node = 0, i; u32 total_num_lanes = 0; + int already_configured; u8 init_dp_regmap = 0; u32 phy_type; @@ -2096,26 +2336,6 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) cdns_phy->dev = dev; cdns_phy->init_data = data; - cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); - if (IS_ERR(cdns_phy->phy_rst)) { - dev_err(dev, "%s: failed to get reset\n", - dev->of_node->full_name); - return PTR_ERR(cdns_phy->phy_rst); - } - - cdns_phy->apb_rst = devm_reset_control_get_optional(dev, "torrent_apb"); - if (IS_ERR(cdns_phy->apb_rst)) { - dev_err(dev, "%s: failed to get apb reset\n", - dev->of_node->full_name); - return PTR_ERR(cdns_phy->apb_rst); - } - - cdns_phy->clk = devm_clk_get(dev, "refclk"); - if (IS_ERR(cdns_phy->clk)) { - dev_err(dev, "phy ref clock not found\n"); - return PTR_ERR(cdns_phy->clk); - } - cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(cdns_phy->sd_base)) return PTR_ERR(cdns_phy->sd_base); @@ -2134,21 +2354,24 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) if (ret) return ret; - ret = clk_prepare_enable(cdns_phy->clk); - if (ret) { - dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); + ret = cdns_torrent_clk_register(cdns_phy); + if (ret) return ret; - } - cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); - if (!(cdns_phy->ref_clk_rate)) { - dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); - clk_disable_unprepare(cdns_phy->clk); - return -EINVAL; - } + regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured); - /* Enable APB */ - reset_control_deassert(cdns_phy->apb_rst); + if (!already_configured) { + ret = cdns_torrent_reset(cdns_phy); + if (ret) + goto clk_cleanup; + + ret = cdns_torrent_clk(cdns_phy); + if (ret) + goto clk_cleanup; + + /* Enable APB */ + reset_control_deassert(cdns_phy->apb_rst); + } for_each_available_child_of_node(dev->of_node, child) { struct phy *gphy; @@ -2218,7 +2441,10 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) of_property_read_u32(child, "cdns,ssc-mode", &cdns_phy->phys[node].ssc_mode); - gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); + if (!already_configured) + gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); + else + gphy = devm_phy_create(dev, child, &noop_ops); if (IS_ERR(gphy)) { ret = PTR_ERR(gphy); goto put_child; @@ -2302,7 +2528,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) goto put_lnk_rst; } - if (cdns_phy->nsubnodes > 1) { + if (cdns_phy->nsubnodes > 1 && !already_configured) { ret = cdns_torrent_phy_configure_multilink(cdns_phy); if (ret) goto put_lnk_rst; @@ -2324,6 +2550,8 @@ put_lnk_rst: of_node_put(child); reset_control_assert(cdns_phy->apb_rst); clk_disable_unprepare(cdns_phy->clk); +clk_cleanup: + cdns_torrent_clk_cleanup(cdns_phy); return ret; } @@ -2340,6 +2568,7 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev) } clk_disable_unprepare(cdns_phy->clk); + cdns_torrent_clk_cleanup(cdns_phy); return 0; } @@ -2455,8 +2684,6 @@ static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, - {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL}, {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, @@ -2464,7 +2691,9 @@ static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, - {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} + {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, + {0x007F, CMN_TXPUCAL_TUNE}, + {0x007F, CMN_TXPDCAL_TUNE} }; static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = { @@ -2507,13 +2736,28 @@ static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { }; /* USB 100 MHz Ref clk, no SSC */ -static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { +static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { + {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, + {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, {0x0003, CMN_PLL0_VCOCAL_TCTRL}, {0x0003, CMN_PLL1_VCOCAL_TCTRL}, {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} }; +static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = { + .reg_pairs = sl_usb_100_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), +}; + +static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { + {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, + {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, + {0x007F, CMN_TXPUCAL_TUNE}, + {0x007F, CMN_TXPDCAL_TUNE} +}; + static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { {0x02FF, TX_PSC_A0}, {0x06AF, TX_PSC_A1}, @@ -2645,12 +2889,22 @@ static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { }; /* SGMII 100 MHz Ref clk, no SSC */ -static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { +static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { + {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, + {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL}, - {0x3700, CMN_DIAG_BIAS_OVRD1}, - {0x0008, CMN_TXPUCAL_TUNE}, - {0x0008, CMN_TXPDCAL_TUNE} + {0x0003, CMN_PLL1_VCOCAL_TCTRL} +}; + +static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = { + .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), +}; + +static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { + {0x007F, CMN_TXPUCAL_TUNE}, + {0x007F, CMN_TXPDCAL_TUNE} }; static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { @@ -2661,6 +2915,15 @@ static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { {0x00B3, DRV_DIAG_TX_DRV} }; +static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { + {0x00F3, TX_PSC_A0}, + {0x04A2, TX_PSC_A2}, + {0x04A2, TX_PSC_A3}, + {0x0000, TX_TXCC_CPOST_MULT_00}, + {0x00B3, DRV_DIAG_TX_DRV}, + {0x4000, XCVR_DIAG_RXCLK_CTRL}, +}; + static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { {0x091D, RX_PSC_A0}, {0x0900, RX_PSC_A2}, @@ -2689,6 +2952,11 @@ static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), }; +static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = { + .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs, + .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs), +}; + static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), @@ -2736,17 +3004,14 @@ static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, - {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL}, {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, - {0x3700, CMN_DIAG_BIAS_OVRD1}, - {0x0008, CMN_TXPUCAL_TUNE}, - {0x0008, CMN_TXPDCAL_TUNE} + {0x007F, CMN_TXPUCAL_TUNE}, + {0x007F, CMN_TXPDCAL_TUNE} }; static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { @@ -2755,19 +3020,43 @@ static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { }; /* QSGMII 100 MHz Ref clk, no SSC */ -static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { +static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { + {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, + {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, {0x0003, CMN_PLL0_VCOCAL_TCTRL}, {0x0003, CMN_PLL1_VCOCAL_TCTRL} }; +static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = { + .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs, + .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), +}; + +static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { + {0x007F, CMN_TXPUCAL_TUNE}, + {0x007F, CMN_TXPDCAL_TUNE} +}; + static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { {0x00F3, TX_PSC_A0}, {0x04A2, TX_PSC_A2}, {0x04A2, TX_PSC_A3}, {0x0000, TX_TXCC_CPOST_MULT_00}, + {0x0011, TX_TXCC_MGNFS_MULT_100}, {0x0003, DRV_DIAG_TX_DRV} }; +static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { + {0x00F3, TX_PSC_A0}, + {0x04A2, TX_PSC_A2}, + {0x04A2, TX_PSC_A3}, + {0x0000, TX_TXCC_CPOST_MULT_00}, + {0x0011, TX_TXCC_MGNFS_MULT_100}, + {0x0003, DRV_DIAG_TX_DRV}, + {0x4000, XCVR_DIAG_RXCLK_CTRL}, +}; + static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { {0x091D, RX_PSC_A0}, {0x0900, RX_PSC_A2}, @@ -2796,6 +3085,11 @@ static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), }; +static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = { + .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs, + .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs), +}; + static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), @@ -2843,14 +3137,14 @@ static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, - {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL}, {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, - {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, + {0x007F, CMN_TXPUCAL_TUNE}, + {0x007F, CMN_TXPDCAL_TUNE} }; static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { @@ -2922,8 +3216,6 @@ static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, - {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL}, {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, @@ -2979,8 +3271,6 @@ static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, - {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL}, {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, @@ -2996,8 +3286,9 @@ static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { - {0x0003, CMN_PLL0_VCOCAL_TCTRL}, - {0x0003, CMN_PLL1_VCOCAL_TCTRL} + {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, + {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, + {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} }; static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { @@ -3198,8 +3489,8 @@ static const struct cdns_torrent_data cdns_map_torrent = { .cmn_vals = { [TYPE_PCIE] = { [TYPE_NONE] = { - [NO_SSC] = &pcie_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, }, [TYPE_SGMII] = { @@ -3220,7 +3511,7 @@ static const struct cdns_torrent_data cdns_map_torrent = { }, [TYPE_SGMII] = { [TYPE_NONE] = { - [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, }, [TYPE_PCIE] = { [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, @@ -3235,7 +3526,7 @@ static const struct cdns_torrent_data cdns_map_torrent = { }, [TYPE_QSGMII] = { [TYPE_NONE] = { - [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, }, [TYPE_PCIE] = { [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, @@ -3250,8 +3541,8 @@ static const struct cdns_torrent_data cdns_map_torrent = { }, [TYPE_USB] = { [TYPE_NONE] = { - [NO_SSC] = &usb_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, }, [TYPE_PCIE] = { @@ -3260,13 +3551,13 @@ static const struct cdns_torrent_data cdns_map_torrent = { [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, }, [TYPE_SGMII] = { - [NO_SSC] = &usb_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, }, [TYPE_QSGMII] = { - [NO_SSC] = &usb_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, }, }, @@ -3607,8 +3898,8 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { .cmn_vals = { [TYPE_PCIE] = { [TYPE_NONE] = { - [NO_SSC] = &pcie_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, + [NO_SSC] = NULL, + [EXTERNAL_SSC] = NULL, [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, }, [TYPE_SGMII] = { @@ -3629,7 +3920,7 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { }, [TYPE_SGMII] = { [TYPE_NONE] = { - [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, }, [TYPE_PCIE] = { [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, @@ -3644,7 +3935,7 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { }, [TYPE_QSGMII] = { [TYPE_NONE] = { - [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, }, [TYPE_PCIE] = { [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, @@ -3659,8 +3950,8 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { }, [TYPE_USB] = { [TYPE_NONE] = { - [NO_SSC] = &usb_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, }, [TYPE_PCIE] = { @@ -3669,13 +3960,13 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, }, [TYPE_SGMII] = { - [NO_SSC] = &usb_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, }, [TYPE_QSGMII] = { - [NO_SSC] = &usb_100_no_ssc_cmn_vals, - [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, + [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, + [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, }, }, @@ -3705,32 +3996,32 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = { }, [TYPE_SGMII] = { [TYPE_NONE] = { - [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, }, [TYPE_PCIE] = { - [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, - [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, - [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, }, [TYPE_USB] = { - [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, - [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, - [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, + [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, }, }, [TYPE_QSGMII] = { [TYPE_NONE] = { - [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, }, [TYPE_PCIE] = { - [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, - [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, - [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, }, [TYPE_USB] = { - [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, - [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, - [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, + [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, + [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, + [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, }, }, [TYPE_USB] = { diff --git a/drivers/phy/hisilicon/phy-hi6220-usb.c b/drivers/phy/hisilicon/phy-hi6220-usb.c index be05292df8b8..e92ba78da4c8 100644 --- a/drivers/phy/hisilicon/phy-hi6220-usb.c +++ b/drivers/phy/hisilicon/phy-hi6220-usb.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2015 Linaro Ltd. - * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 HiSilicon Limited. */ #include <linux/mfd/syscon.h> diff --git a/drivers/phy/hisilicon/phy-hix5hd2-sata.c b/drivers/phy/hisilicon/phy-hix5hd2-sata.c index c67b78cd2602..b0f99a9ac857 100644 --- a/drivers/phy/hisilicon/phy-hix5hd2-sata.c +++ b/drivers/phy/hisilicon/phy-hix5hd2-sata.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 Linaro Ltd. - * Copyright (c) 2014 Hisilicon Limited. + * Copyright (c) 2014 HiSilicon Limited. */ #include <linux/delay.h> diff --git a/drivers/phy/ingenic/phy-ingenic-usb.c b/drivers/phy/ingenic/phy-ingenic-usb.c index ea127b177f46..28c28d816484 100644 --- a/drivers/phy/ingenic/phy-ingenic-usb.c +++ b/drivers/phy/ingenic/phy-ingenic-usb.c @@ -352,8 +352,8 @@ static int ingenic_usb_phy_probe(struct platform_device *pdev) } priv->phy = devm_phy_create(dev, NULL, &ingenic_usb_phy_ops); - if (IS_ERR(priv)) - return PTR_ERR(priv); + if (IS_ERR(priv->phy)) + return PTR_ERR(priv->phy); phy_set_drvdata(priv->phy, priv); diff --git a/drivers/phy/intel/phy-intel-lgm-combo.c b/drivers/phy/intel/phy-intel-lgm-combo.c index 360b1eb2ebd6..157683d10367 100644 --- a/drivers/phy/intel/phy-intel-lgm-combo.c +++ b/drivers/phy/intel/phy-intel-lgm-combo.c @@ -462,7 +462,7 @@ static int intel_cbphy_fwnode_parse(struct intel_combo_phy *cbphy) /* * syscfg and hsiocfg variables stores the handle of the registers set - * in which ComboPhy subsytem specific registers are subset. Using + * in which ComboPhy subsystem specific registers are subset. Using * Register map framework to access the registers set. */ ret = fwnode_property_get_reference_args(fwnode, "intel,syscfg", NULL, diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 6c96f2bf5266..bdb87c976243 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -3,8 +3,8 @@ # Phy drivers for Marvell platforms # config ARMADA375_USBCLUSTER_PHY - def_bool y - depends on MACH_ARMADA_375 || COMPILE_TEST + bool "Armada 375 USB cluster PHY support" if COMPILE_TEST + default y if MACH_ARMADA_375 depends on OF && HAS_IOMEM select GENERIC_PHY @@ -67,6 +67,14 @@ config PHY_MVEBU_CP110_COMPHY lanes can be used by various controllers (Ethernet, sata, usb, PCIe...). +config PHY_MVEBU_CP110_UTMI + tristate "Marvell CP110 UTMI driver" + depends on ARCH_MVEBU || COMPILE_TEST + depends on OF && USB_COMMON + select GENERIC_PHY + help + Enable this to support Marvell CP110 UTMI PHY driver. + config PHY_MVEBU_SATA def_bool y depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile index 7f296ef02829..90862c4daa26 100644 --- a/drivers/phy/marvell/Makefile +++ b/drivers/phy/marvell/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o +obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c new file mode 100644 index 000000000000..08d178a4dc13 --- /dev/null +++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Marvell + * + * Authors: + * Konstantin Porotchkin <kostap@marvell.com> + * + * Marvell CP110 UTMI PHY driver + */ + +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/usb/of.h> +#include <linux/usb/otg.h> + +#define UTMI_PHY_PORTS 2 + +/* CP110 UTMI register macro definetions */ +#define SYSCON_USB_CFG_REG 0x420 +#define USB_CFG_DEVICE_EN_MASK BIT(0) +#define USB_CFG_DEVICE_MUX_OFFSET 1 +#define USB_CFG_DEVICE_MUX_MASK BIT(1) +#define USB_CFG_PLL_MASK BIT(25) + +#define SYSCON_UTMI_CFG_REG(id) (0x440 + (id) * 4) +#define UTMI_PHY_CFG_PU_MASK BIT(5) + +#define UTMI_PLL_CTRL_REG 0x0 +#define PLL_REFDIV_OFFSET 0 +#define PLL_REFDIV_MASK GENMASK(6, 0) +#define PLL_REFDIV_VAL 0x5 +#define PLL_FBDIV_OFFSET 16 +#define PLL_FBDIV_MASK GENMASK(24, 16) +#define PLL_FBDIV_VAL 0x60 +#define PLL_SEL_LPFR_MASK GENMASK(29, 28) +#define PLL_RDY BIT(31) +#define UTMI_CAL_CTRL_REG 0x8 +#define IMPCAL_VTH_OFFSET 8 +#define IMPCAL_VTH_MASK GENMASK(10, 8) +#define IMPCAL_VTH_VAL 0x7 +#define IMPCAL_DONE BIT(23) +#define PLLCAL_DONE BIT(31) +#define UTMI_TX_CH_CTRL_REG 0xC +#define DRV_EN_LS_OFFSET 12 +#define DRV_EN_LS_MASK GENMASK(15, 12) +#define IMP_SEL_LS_OFFSET 16 +#define IMP_SEL_LS_MASK GENMASK(19, 16) +#define TX_AMP_OFFSET 20 +#define TX_AMP_MASK GENMASK(22, 20) +#define TX_AMP_VAL 0x4 +#define UTMI_RX_CH_CTRL0_REG 0x14 +#define SQ_DET_EN BIT(15) +#define SQ_ANA_DTC_SEL BIT(28) +#define UTMI_RX_CH_CTRL1_REG 0x18 +#define SQ_AMP_CAL_OFFSET 0 +#define SQ_AMP_CAL_MASK GENMASK(2, 0) +#define SQ_AMP_CAL_VAL 1 +#define SQ_AMP_CAL_EN BIT(3) +#define UTMI_CTRL_STATUS0_REG 0x24 +#define SUSPENDM BIT(22) +#define TEST_SEL BIT(25) +#define UTMI_CHGDTC_CTRL_REG 0x38 +#define VDAT_OFFSET 8 +#define VDAT_MASK GENMASK(9, 8) +#define VDAT_VAL 1 +#define VSRC_OFFSET 10 +#define VSRC_MASK GENMASK(11, 10) +#define VSRC_VAL 1 + +#define PLL_LOCK_DELAY_US 10000 +#define PLL_LOCK_TIMEOUT_US 1000000 + +#define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000) + +/** + * struct mvebu_cp110_utmi - PHY driver data + * + * @regs: PHY registers + * @syscom: Regmap with system controller registers + * @dev: device driver handle + * @caps: PHY capabilities + */ +struct mvebu_cp110_utmi { + void __iomem *regs; + struct regmap *syscon; + struct device *dev; + const struct phy_ops *ops; +}; + +/** + * struct mvebu_cp110_utmi_port - PHY port data + * + * @priv: PHY driver data + * @id: PHY port ID + * @dr_mode: PHY connection: USB_DR_MODE_HOST or USB_DR_MODE_PERIPHERAL + */ +struct mvebu_cp110_utmi_port { + struct mvebu_cp110_utmi *priv; + u32 id; + enum usb_dr_mode dr_mode; +}; + +static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port *port) +{ + u32 reg; + + /* + * Setup PLL. + * The reference clock is the frequency of quartz resonator + * connected to pins REFCLK_XIN and REFCLK_XOUT of the SoC. + * Register init values are matching the 40MHz default clock. + * The crystal used for all platform boards is now 25MHz. + * See the functional specification for details. + */ + reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG); + reg &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK | PLL_SEL_LPFR_MASK); + reg |= (PLL_REFDIV_VAL << PLL_REFDIV_OFFSET) | + (PLL_FBDIV_VAL << PLL_FBDIV_OFFSET); + writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG); + + /* Impedance Calibration Threshold Setting */ + reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG); + reg &= ~IMPCAL_VTH_MASK; + reg |= IMPCAL_VTH_VAL << IMPCAL_VTH_OFFSET; + writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG); + + /* Set LS TX driver strength coarse control */ + reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG); + reg &= ~TX_AMP_MASK; + reg |= TX_AMP_VAL << TX_AMP_OFFSET; + writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG); + + /* Disable SQ and enable analog squelch detect */ + reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG); + reg &= ~SQ_DET_EN; + reg |= SQ_ANA_DTC_SEL; + writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG); + + /* + * Set External squelch calibration number and + * enable the External squelch calibration + */ + reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG); + reg &= ~SQ_AMP_CAL_MASK; + reg |= (SQ_AMP_CAL_VAL << SQ_AMP_CAL_OFFSET) | SQ_AMP_CAL_EN; + writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG); + + /* + * Set Control VDAT Reference Voltage - 0.325V and + * Control VSRC Reference Voltage - 0.6V + */ + reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG); + reg &= ~(VDAT_MASK | VSRC_MASK); + reg |= (VDAT_VAL << VDAT_OFFSET) | (VSRC_VAL << VSRC_OFFSET); + writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG); +} + +static int mvebu_cp110_utmi_phy_power_off(struct phy *phy) +{ + struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy); + struct mvebu_cp110_utmi *utmi = port->priv; + int i; + + /* Power down UTMI PHY port */ + regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id), + UTMI_PHY_CFG_PU_MASK); + + for (i = 0; i < UTMI_PHY_PORTS; i++) { + int test = regmap_test_bits(utmi->syscon, + SYSCON_UTMI_CFG_REG(i), + UTMI_PHY_CFG_PU_MASK); + /* skip PLL shutdown if there are active UTMI PHY ports */ + if (test != 0) + return 0; + } + + /* PLL Power down if all UTMI PHYs are down */ + regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK); + + return 0; +} + +static int mvebu_cp110_utmi_phy_power_on(struct phy *phy) +{ + struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy); + struct mvebu_cp110_utmi *utmi = port->priv; + struct device *dev = &phy->dev; + int ret; + u32 reg; + + /* It is necessary to power off UTMI before configuration */ + ret = mvebu_cp110_utmi_phy_power_off(phy); + if (ret) { + dev_err(dev, "UTMI power OFF before power ON failed\n"); + return ret; + } + + /* + * If UTMI port is connected to USB Device controller, + * configure the USB MUX prior to UTMI PHY initialization. + * The single USB device controller can be connected + * to UTMI0 or to UTMI1 PHY port, but not to both. + */ + if (port->dr_mode == USB_DR_MODE_PERIPHERAL) { + regmap_update_bits(utmi->syscon, SYSCON_USB_CFG_REG, + USB_CFG_DEVICE_EN_MASK | USB_CFG_DEVICE_MUX_MASK, + USB_CFG_DEVICE_EN_MASK | + (port->id << USB_CFG_DEVICE_MUX_OFFSET)); + } + + /* Set Test suspendm mode and enable Test UTMI select */ + reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); + reg |= SUSPENDM | TEST_SEL; + writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); + + /* Wait for UTMI power down */ + mdelay(1); + + /* PHY port setup first */ + mvebu_cp110_utmi_port_setup(port); + + /* Power UP UTMI PHY */ + regmap_set_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id), + UTMI_PHY_CFG_PU_MASK); + + /* Disable Test UTMI select */ + reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); + reg &= ~TEST_SEL; + writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); + + /* Wait for impedance calibration */ + ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg, + reg & IMPCAL_DONE, + PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US); + if (ret) { + dev_err(dev, "Failed to end UTMI impedance calibration\n"); + return ret; + } + + /* Wait for PLL calibration */ + ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg, + reg & PLLCAL_DONE, + PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US); + if (ret) { + dev_err(dev, "Failed to end UTMI PLL calibration\n"); + return ret; + } + + /* Wait for PLL ready */ + ret = readl_poll_timeout(PORT_REGS(port) + UTMI_PLL_CTRL_REG, reg, + reg & PLL_RDY, + PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US); + if (ret) { + dev_err(dev, "PLL is not ready\n"); + return ret; + } + + /* PLL Power up */ + regmap_set_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK); + + return 0; +} + +static const struct phy_ops mvebu_cp110_utmi_phy_ops = { + .power_on = mvebu_cp110_utmi_phy_power_on, + .power_off = mvebu_cp110_utmi_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct of_device_id mvebu_cp110_utmi_of_match[] = { + { .compatible = "marvell,cp110-utmi-phy" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mvebu_cp110_utmi_of_match); + +static int mvebu_cp110_utmi_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mvebu_cp110_utmi *utmi; + struct phy_provider *provider; + struct device_node *child; + u32 usb_devices = 0; + + utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL); + if (!utmi) + return -ENOMEM; + + utmi->dev = dev; + + /* Get system controller region */ + utmi->syscon = syscon_regmap_lookup_by_phandle(dev->of_node, + "marvell,system-controller"); + if (IS_ERR(utmi->syscon)) { + dev_err(dev, "Missing UTMI system controller\n"); + return PTR_ERR(utmi->syscon); + } + + /* Get UTMI memory region */ + utmi->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(utmi->regs)) + return PTR_ERR(utmi->regs); + + for_each_available_child_of_node(dev->of_node, child) { + struct mvebu_cp110_utmi_port *port; + struct phy *phy; + int ret; + u32 port_id; + + ret = of_property_read_u32(child, "reg", &port_id); + if ((ret < 0) || (port_id >= UTMI_PHY_PORTS)) { + dev_err(dev, + "invalid 'reg' property on child %pOF\n", + child); + continue; + } + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) { + of_node_put(child); + return -ENOMEM; + } + + port->dr_mode = of_usb_get_dr_mode_by_phy(child, -1); + if ((port->dr_mode != USB_DR_MODE_HOST) && + (port->dr_mode != USB_DR_MODE_PERIPHERAL)) { + dev_err(&pdev->dev, + "Missing dual role setting of the port%d, will use HOST mode\n", + port_id); + port->dr_mode = USB_DR_MODE_HOST; + } + + if (port->dr_mode == USB_DR_MODE_PERIPHERAL) { + usb_devices++; + if (usb_devices > 1) { + dev_err(dev, + "Single USB device allowed! Port%d will use HOST mode\n", + port_id); + port->dr_mode = USB_DR_MODE_HOST; + } + } + + /* Retrieve PHY capabilities */ + utmi->ops = &mvebu_cp110_utmi_phy_ops; + + /* Instantiate the PHY */ + phy = devm_phy_create(dev, child, utmi->ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create the UTMI PHY\n"); + of_node_put(child); + return PTR_ERR(phy); + } + + port->priv = utmi; + port->id = port_id; + phy_set_drvdata(phy, port); + + /* Ensure the PHY is powered off */ + mvebu_cp110_utmi_phy_power_off(phy); + } + + dev_set_drvdata(dev, utmi); + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static struct platform_driver mvebu_cp110_utmi_driver = { + .probe = mvebu_cp110_utmi_phy_probe, + .driver = { + .name = "mvebu-cp110-utmi-phy", + .of_match_table = mvebu_cp110_utmi_of_match, + }, +}; +module_platform_driver(mvebu_cp110_utmi_driver); + +MODULE_AUTHOR("Konstatin Porotchkin <kostap@marvell.com>"); +MODULE_DESCRIPTION("Marvell Armada CP110 UTMI PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/microchip/Kconfig b/drivers/phy/microchip/Kconfig new file mode 100644 index 000000000000..3728a284bf64 --- /dev/null +++ b/drivers/phy/microchip/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Microchip devices +# + +config PHY_SPARX5_SERDES + tristate "Microchip Sparx5 SerDes PHY driver" + select GENERIC_PHY + depends on ARCH_SPARX5 || COMPILE_TEST + depends on OF + depends on HAS_IOMEM + help + Enable this for support of the 10G/25G SerDes on Microchip Sparx5. diff --git a/drivers/phy/microchip/Makefile b/drivers/phy/microchip/Makefile new file mode 100644 index 000000000000..7b98345712aa --- /dev/null +++ b/drivers/phy/microchip/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the Microchip phy drivers. +# + +obj-$(CONFIG_PHY_SPARX5_SERDES) := sparx5_serdes.o diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c new file mode 100644 index 000000000000..c8a7d0927ced --- /dev/null +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -0,0 +1,2513 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Microchip Sparx5 Switch SerDes driver + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * The Sparx5 Chip Register Model can be browsed at this location: + * https://github.com/microchip-ung/sparx-5_reginfo + * and the datasheet is available here: + * https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf + */ +#include <linux/printk.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/netdevice.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/phy.h> +#include <linux/phy/phy.h> + +#include "sparx5_serdes.h" + +#define SPX5_CMU_MAX 14 + +#define SPX5_SERDES_10G_START 13 +#define SPX5_SERDES_25G_START 25 + +enum sparx5_10g28cmu_mode { + SPX5_SD10G28_CMU_MAIN = 0, + SPX5_SD10G28_CMU_AUX1 = 1, + SPX5_SD10G28_CMU_AUX2 = 3, + SPX5_SD10G28_CMU_NONE = 4, +}; + +enum sparx5_sd25g28_mode_preset_type { + SPX5_SD25G28_MODE_PRESET_25000, + SPX5_SD25G28_MODE_PRESET_10000, + SPX5_SD25G28_MODE_PRESET_5000, + SPX5_SD25G28_MODE_PRESET_SD_2G5, + SPX5_SD25G28_MODE_PRESET_1000BASEX, +}; + +enum sparx5_sd10g28_mode_preset_type { + SPX5_SD10G28_MODE_PRESET_10000, + SPX5_SD10G28_MODE_PRESET_SFI_5000_6G, + SPX5_SD10G28_MODE_PRESET_SFI_5000_10G, + SPX5_SD10G28_MODE_PRESET_QSGMII, + SPX5_SD10G28_MODE_PRESET_SD_2G5, + SPX5_SD10G28_MODE_PRESET_1000BASEX, +}; + +struct sparx5_serdes_io_resource { + enum sparx5_serdes_target id; + phys_addr_t offset; +}; + +struct sparx5_sd25g28_mode_preset { + u8 bitwidth; + u8 tx_pre_div; + u8 fifo_ck_div; + u8 pre_divsel; + u8 vco_div_mode; + u8 sel_div; + u8 ck_bitwidth; + u8 subrate; + u8 com_txcal_en; + u8 com_tx_reserve_msb; + u8 com_tx_reserve_lsb; + u8 cfg_itx_ipcml_base; + u8 tx_reserve_lsb; + u8 tx_reserve_msb; + u8 bw; + u8 rxterm; + u8 dfe_tap; + u8 dfe_enable; + bool txmargin; + u8 cfg_ctle_rstn; + u8 r_dfe_rstn; + u8 cfg_pi_bw_3_0; + u8 tx_tap_dly; + u8 tx_tap_adv; +}; + +struct sparx5_sd25g28_media_preset { + u8 cfg_eq_c_force_3_0; + u8 cfg_vga_ctrl_byp_4_0; + u8 cfg_eq_r_force_3_0; + u8 cfg_en_adv; + u8 cfg_en_main; + u8 cfg_en_dly; + u8 cfg_tap_adv_3_0; + u8 cfg_tap_main; + u8 cfg_tap_dly_4_0; + u8 cfg_alos_thr_2_0; +}; + +struct sparx5_sd25g28_args { + u8 if_width; /* UDL if-width: 10/16/20/32/64 */ + bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */ + enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */ + bool no_pwrcycle:1; /* Omit initial power-cycle */ + bool txinvert:1; /* Enable inversion of output data */ + bool rxinvert:1; /* Enable inversion of input data */ + u16 txswing; /* Set output level */ + u8 rate; /* Rate of network interface */ + u8 pi_bw_gen1; + u8 duty_cycle; /* Set output level to half/full */ + bool mute:1; /* Mute Output Buffer */ + bool reg_rst:1; + u8 com_pll_reserve; +}; + +struct sparx5_sd25g28_params { + u8 reg_rst; + u8 cfg_jc_byp; + u8 cfg_common_reserve_7_0; + u8 r_reg_manual; + u8 r_d_width_ctrl_from_hwt; + u8 r_d_width_ctrl_2_0; + u8 r_txfifo_ck_div_pmad_2_0; + u8 r_rxfifo_ck_div_pmad_2_0; + u8 cfg_pll_lol_set; + u8 cfg_vco_div_mode_1_0; + u8 cfg_pre_divsel_1_0; + u8 cfg_sel_div_3_0; + u8 cfg_vco_start_code_3_0; + u8 cfg_pma_tx_ck_bitwidth_2_0; + u8 cfg_tx_prediv_1_0; + u8 cfg_rxdiv_sel_2_0; + u8 cfg_tx_subrate_2_0; + u8 cfg_rx_subrate_2_0; + u8 r_multi_lane_mode; + u8 cfg_cdrck_en; + u8 cfg_dfeck_en; + u8 cfg_dfe_pd; + u8 cfg_dfedmx_pd; + u8 cfg_dfetap_en_5_1; + u8 cfg_dmux_pd; + u8 cfg_dmux_clk_pd; + u8 cfg_erramp_pd; + u8 cfg_pi_dfe_en; + u8 cfg_pi_en; + u8 cfg_pd_ctle; + u8 cfg_summer_en; + u8 cfg_pmad_ck_pd; + u8 cfg_pd_clk; + u8 cfg_pd_cml; + u8 cfg_pd_driver; + u8 cfg_rx_reg_pu; + u8 cfg_pd_rms_det; + u8 cfg_dcdr_pd; + u8 cfg_ecdr_pd; + u8 cfg_pd_sq; + u8 cfg_itx_ipdriver_base_2_0; + u8 cfg_tap_dly_4_0; + u8 cfg_tap_main; + u8 cfg_en_main; + u8 cfg_tap_adv_3_0; + u8 cfg_en_adv; + u8 cfg_en_dly; + u8 cfg_iscan_en; + u8 l1_pcs_en_fast_iscan; + u8 l0_cfg_bw_1_0; + u8 l0_cfg_txcal_en; + u8 cfg_en_dummy; + u8 cfg_pll_reserve_3_0; + u8 l0_cfg_tx_reserve_15_8; + u8 l0_cfg_tx_reserve_7_0; + u8 cfg_tx_reserve_15_8; + u8 cfg_tx_reserve_7_0; + u8 cfg_bw_1_0; + u8 cfg_txcal_man_en; + u8 cfg_phase_man_4_0; + u8 cfg_quad_man_1_0; + u8 cfg_txcal_shift_code_5_0; + u8 cfg_txcal_valid_sel_3_0; + u8 cfg_txcal_en; + u8 cfg_cdr_kf_2_0; + u8 cfg_cdr_m_7_0; + u8 cfg_pi_bw_3_0; + u8 cfg_pi_steps_1_0; + u8 cfg_dis_2ndorder; + u8 cfg_ctle_rstn; + u8 r_dfe_rstn; + u8 cfg_alos_thr_2_0; + u8 cfg_itx_ipcml_base_1_0; + u8 cfg_rx_reserve_7_0; + u8 cfg_rx_reserve_15_8; + u8 cfg_rxterm_2_0; + u8 cfg_fom_selm; + u8 cfg_rx_sp_ctle_1_0; + u8 cfg_isel_ctle_1_0; + u8 cfg_vga_ctrl_byp_4_0; + u8 cfg_vga_byp; + u8 cfg_agc_adpt_byp; + u8 cfg_eqr_byp; + u8 cfg_eqr_force_3_0; + u8 cfg_eqc_force_3_0; + u8 cfg_sum_setcm_en; + u8 cfg_init_pos_iscan_6_0; + u8 cfg_init_pos_ipi_6_0; + u8 cfg_dfedig_m_2_0; + u8 cfg_en_dfedig; + u8 cfg_pi_DFE_en; + u8 cfg_tx2rx_lp_en; + u8 cfg_txlb_en; + u8 cfg_rx2tx_lp_en; + u8 cfg_rxlb_en; + u8 r_tx_pol_inv; + u8 r_rx_pol_inv; +}; + +struct sparx5_sd10g28_media_preset { + u8 cfg_en_adv; + u8 cfg_en_main; + u8 cfg_en_dly; + u8 cfg_tap_adv_3_0; + u8 cfg_tap_main; + u8 cfg_tap_dly_4_0; + u8 cfg_vga_ctrl_3_0; + u8 cfg_vga_cp_2_0; + u8 cfg_eq_res_3_0; + u8 cfg_eq_r_byp; + u8 cfg_eq_c_force_3_0; + u8 cfg_alos_thr_3_0; +}; + +struct sparx5_sd10g28_mode_preset { + u8 bwidth; /* interface width: 10/16/20/32/64 */ + enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */ + u8 rate; /* Rate of network interface */ + u8 dfe_tap; + u8 dfe_enable; + u8 pi_bw_gen1; + u8 duty_cycle; /* Set output level to half/full */ +}; + +struct sparx5_sd10g28_args { + bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */ + bool no_pwrcycle:1; /* Omit initial power-cycle */ + bool txinvert:1; /* Enable inversion of output data */ + bool rxinvert:1; /* Enable inversion of input data */ + bool txmargin:1; /* Set output level to half/full */ + u16 txswing; /* Set output level */ + bool mute:1; /* Mute Output Buffer */ + bool is_6g:1; + bool reg_rst:1; +}; + +struct sparx5_sd10g28_params { + u8 cmu_sel; + u8 is_6g; + u8 skip_cmu_cfg; + u8 cfg_lane_reserve_7_0; + u8 cfg_ssc_rtl_clk_sel; + u8 cfg_lane_reserve_15_8; + u8 cfg_txrate_1_0; + u8 cfg_rxrate_1_0; + u8 r_d_width_ctrl_2_0; + u8 cfg_pma_tx_ck_bitwidth_2_0; + u8 cfg_rxdiv_sel_2_0; + u8 r_pcs2pma_phymode_4_0; + u8 cfg_lane_id_2_0; + u8 cfg_cdrck_en; + u8 cfg_dfeck_en; + u8 cfg_dfe_pd; + u8 cfg_dfetap_en_5_1; + u8 cfg_erramp_pd; + u8 cfg_pi_DFE_en; + u8 cfg_pi_en; + u8 cfg_pd_ctle; + u8 cfg_summer_en; + u8 cfg_pd_rx_cktree; + u8 cfg_pd_clk; + u8 cfg_pd_cml; + u8 cfg_pd_driver; + u8 cfg_rx_reg_pu; + u8 cfg_d_cdr_pd; + u8 cfg_pd_sq; + u8 cfg_rxdet_en; + u8 cfg_rxdet_str; + u8 r_multi_lane_mode; + u8 cfg_en_adv; + u8 cfg_en_main; + u8 cfg_en_dly; + u8 cfg_tap_adv_3_0; + u8 cfg_tap_main; + u8 cfg_tap_dly_4_0; + u8 cfg_vga_ctrl_3_0; + u8 cfg_vga_cp_2_0; + u8 cfg_eq_res_3_0; + u8 cfg_eq_r_byp; + u8 cfg_eq_c_force_3_0; + u8 cfg_en_dfedig; + u8 cfg_sum_setcm_en; + u8 cfg_en_preemph; + u8 cfg_itx_ippreemp_base_1_0; + u8 cfg_itx_ipdriver_base_2_0; + u8 cfg_ibias_tune_reserve_5_0; + u8 cfg_txswing_half; + u8 cfg_dis_2nd_order; + u8 cfg_rx_ssc_lh; + u8 cfg_pi_floop_steps_1_0; + u8 cfg_pi_ext_dac_23_16; + u8 cfg_pi_ext_dac_15_8; + u8 cfg_iscan_ext_dac_7_0; + u8 cfg_cdr_kf_gen1_2_0; + u8 cfg_cdr_kf_gen2_2_0; + u8 cfg_cdr_kf_gen3_2_0; + u8 cfg_cdr_kf_gen4_2_0; + u8 r_cdr_m_gen1_7_0; + u8 cfg_pi_bw_gen1_3_0; + u8 cfg_pi_bw_gen2; + u8 cfg_pi_bw_gen3; + u8 cfg_pi_bw_gen4; + u8 cfg_pi_ext_dac_7_0; + u8 cfg_pi_steps; + u8 cfg_mp_max_3_0; + u8 cfg_rstn_dfedig; + u8 cfg_alos_thr_3_0; + u8 cfg_predrv_slewrate_1_0; + u8 cfg_itx_ipcml_base_1_0; + u8 cfg_ip_pre_base_1_0; + u8 r_cdr_m_gen2_7_0; + u8 r_cdr_m_gen3_7_0; + u8 r_cdr_m_gen4_7_0; + u8 r_en_auto_cdr_rstn; + u8 cfg_oscal_afe; + u8 cfg_pd_osdac_afe; + u8 cfg_resetb_oscal_afe[2]; + u8 cfg_center_spreading; + u8 cfg_m_cnt_maxval_4_0; + u8 cfg_ncnt_maxval_7_0; + u8 cfg_ncnt_maxval_10_8; + u8 cfg_ssc_en; + u8 cfg_tx2rx_lp_en; + u8 cfg_txlb_en; + u8 cfg_rx2tx_lp_en; + u8 cfg_rxlb_en; + u8 r_tx_pol_inv; + u8 r_rx_pol_inv; + u8 fx_100; +}; + +static struct sparx5_sd25g28_media_preset media_presets_25g[] = { + { /* ETH_MEDIA_DEFAULT */ + .cfg_en_adv = 0, + .cfg_en_main = 1, + .cfg_en_dly = 0, + .cfg_tap_adv_3_0 = 0, + .cfg_tap_main = 1, + .cfg_tap_dly_4_0 = 0, + .cfg_eq_c_force_3_0 = 0xf, + .cfg_vga_ctrl_byp_4_0 = 4, + .cfg_eq_r_force_3_0 = 12, + .cfg_alos_thr_2_0 = 7, + }, + { /* ETH_MEDIA_SR */ + .cfg_en_adv = 1, + .cfg_en_main = 1, + .cfg_en_dly = 1, + .cfg_tap_adv_3_0 = 0, + .cfg_tap_main = 1, + .cfg_tap_dly_4_0 = 0x10, + .cfg_eq_c_force_3_0 = 0xf, + .cfg_vga_ctrl_byp_4_0 = 8, + .cfg_eq_r_force_3_0 = 4, + .cfg_alos_thr_2_0 = 0, + }, + { /* ETH_MEDIA_DAC */ + .cfg_en_adv = 0, + .cfg_en_main = 1, + .cfg_en_dly = 0, + .cfg_tap_adv_3_0 = 0, + .cfg_tap_main = 1, + .cfg_tap_dly_4_0 = 0, + .cfg_eq_c_force_3_0 = 0xf, + .cfg_vga_ctrl_byp_4_0 = 8, + .cfg_eq_r_force_3_0 = 0xc, + .cfg_alos_thr_2_0 = 0, + }, +}; + +static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = { + { /* SPX5_SD25G28_MODE_PRESET_25000 */ + .bitwidth = 40, + .tx_pre_div = 0, + .fifo_ck_div = 0, + .pre_divsel = 1, + .vco_div_mode = 0, + .sel_div = 15, + .ck_bitwidth = 3, + .subrate = 0, + .com_txcal_en = 0, + .com_tx_reserve_msb = (0x26 << 1), + .com_tx_reserve_lsb = 0xf0, + .cfg_itx_ipcml_base = 0, + .tx_reserve_msb = 0xcc, + .tx_reserve_lsb = 0xfe, + .bw = 3, + .rxterm = 0, + .dfe_enable = 1, + .dfe_tap = 0x1f, + .txmargin = 1, + .cfg_ctle_rstn = 1, + .r_dfe_rstn = 1, + .cfg_pi_bw_3_0 = 0, + .tx_tap_dly = 8, + .tx_tap_adv = 0xc, + }, + { /* SPX5_SD25G28_MODE_PRESET_10000 */ + .bitwidth = 64, + .tx_pre_div = 0, + .fifo_ck_div = 2, + .pre_divsel = 0, + .vco_div_mode = 1, + .sel_div = 9, + .ck_bitwidth = 0, + .subrate = 0, + .com_txcal_en = 1, + .com_tx_reserve_msb = (0x20 << 1), + .com_tx_reserve_lsb = 0x40, + .cfg_itx_ipcml_base = 0, + .tx_reserve_msb = 0x4c, + .tx_reserve_lsb = 0x44, + .bw = 3, + .cfg_pi_bw_3_0 = 0, + .rxterm = 3, + .dfe_enable = 1, + .dfe_tap = 0x1f, + .txmargin = 0, + .cfg_ctle_rstn = 1, + .r_dfe_rstn = 1, + .tx_tap_dly = 0, + .tx_tap_adv = 0, + }, + { /* SPX5_SD25G28_MODE_PRESET_5000 */ + .bitwidth = 64, + .tx_pre_div = 0, + .fifo_ck_div = 2, + .pre_divsel = 0, + .vco_div_mode = 2, + .sel_div = 9, + .ck_bitwidth = 0, + .subrate = 0, + .com_txcal_en = 1, + .com_tx_reserve_msb = (0x20 << 1), + .com_tx_reserve_lsb = 0, + .cfg_itx_ipcml_base = 0, + .tx_reserve_msb = 0xe, + .tx_reserve_lsb = 0x80, + .bw = 0, + .rxterm = 0, + .cfg_pi_bw_3_0 = 6, + .dfe_enable = 0, + .dfe_tap = 0, + .tx_tap_dly = 0, + .tx_tap_adv = 0, + }, + { /* SPX5_SD25G28_MODE_PRESET_SD_2G5 */ + .bitwidth = 10, + .tx_pre_div = 0, + .fifo_ck_div = 0, + .pre_divsel = 0, + .vco_div_mode = 1, + .sel_div = 6, + .ck_bitwidth = 3, + .subrate = 2, + .com_txcal_en = 1, + .com_tx_reserve_msb = (0x26 << 1), + .com_tx_reserve_lsb = (0xf << 4), + .cfg_itx_ipcml_base = 2, + .tx_reserve_msb = 0x8, + .tx_reserve_lsb = 0x8a, + .bw = 0, + .cfg_pi_bw_3_0 = 0, + .rxterm = (1 << 2), + .dfe_enable = 0, + .dfe_tap = 0, + .tx_tap_dly = 0, + .tx_tap_adv = 0, + }, + { /* SPX5_SD25G28_MODE_PRESET_1000BASEX */ + .bitwidth = 10, + .tx_pre_div = 0, + .fifo_ck_div = 1, + .pre_divsel = 0, + .vco_div_mode = 1, + .sel_div = 8, + .ck_bitwidth = 3, + .subrate = 3, + .com_txcal_en = 1, + .com_tx_reserve_msb = (0x26 << 1), + .com_tx_reserve_lsb = 0xf0, + .cfg_itx_ipcml_base = 0, + .tx_reserve_msb = 0x8, + .tx_reserve_lsb = 0xce, + .bw = 0, + .rxterm = 0, + .cfg_pi_bw_3_0 = 0, + .dfe_enable = 0, + .dfe_tap = 0, + .tx_tap_dly = 0, + .tx_tap_adv = 0, + }, +}; + +static struct sparx5_sd10g28_media_preset media_presets_10g[] = { + { /* ETH_MEDIA_DEFAULT */ + .cfg_en_adv = 0, + .cfg_en_main = 1, + .cfg_en_dly = 0, + .cfg_tap_adv_3_0 = 0, + .cfg_tap_main = 1, + .cfg_tap_dly_4_0 = 0, + .cfg_vga_ctrl_3_0 = 5, + .cfg_vga_cp_2_0 = 0, + .cfg_eq_res_3_0 = 0xa, + .cfg_eq_r_byp = 1, + .cfg_eq_c_force_3_0 = 0x8, + .cfg_alos_thr_3_0 = 0x3, + }, + { /* ETH_MEDIA_SR */ + .cfg_en_adv = 1, + .cfg_en_main = 1, + .cfg_en_dly = 1, + .cfg_tap_adv_3_0 = 0, + .cfg_tap_main = 1, + .cfg_tap_dly_4_0 = 0xc, + .cfg_vga_ctrl_3_0 = 0xa, + .cfg_vga_cp_2_0 = 0x4, + .cfg_eq_res_3_0 = 0xa, + .cfg_eq_r_byp = 1, + .cfg_eq_c_force_3_0 = 0xF, + .cfg_alos_thr_3_0 = 0x3, + }, + { /* ETH_MEDIA_DAC */ + .cfg_en_adv = 1, + .cfg_en_main = 1, + .cfg_en_dly = 1, + .cfg_tap_adv_3_0 = 12, + .cfg_tap_main = 1, + .cfg_tap_dly_4_0 = 8, + .cfg_vga_ctrl_3_0 = 0xa, + .cfg_vga_cp_2_0 = 4, + .cfg_eq_res_3_0 = 0xa, + .cfg_eq_r_byp = 1, + .cfg_eq_c_force_3_0 = 0xf, + .cfg_alos_thr_3_0 = 0x0, + } +}; + +static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = { + { /* SPX5_SD10G28_MODE_PRESET_10000 */ + .bwidth = 64, + .cmu_sel = SPX5_SD10G28_CMU_MAIN, + .rate = 0x0, + .dfe_enable = 1, + .dfe_tap = 0x1f, + .pi_bw_gen1 = 0x0, + .duty_cycle = 0x2, + }, + { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */ + .bwidth = 16, + .cmu_sel = SPX5_SD10G28_CMU_MAIN, + .rate = 0x1, + .dfe_enable = 0, + .dfe_tap = 0, + .pi_bw_gen1 = 0x5, + .duty_cycle = 0x0, + }, + { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */ + .bwidth = 64, + .cmu_sel = SPX5_SD10G28_CMU_MAIN, + .rate = 0x1, + .dfe_enable = 0, + .dfe_tap = 0, + .pi_bw_gen1 = 0x5, + .duty_cycle = 0x0, + }, + { /* SPX5_SD10G28_MODE_PRESET_QSGMII */ + .bwidth = 20, + .cmu_sel = SPX5_SD10G28_CMU_AUX1, + .rate = 0x1, + .dfe_enable = 0, + .dfe_tap = 0, + .pi_bw_gen1 = 0x5, + .duty_cycle = 0x0, + }, + { /* SPX5_SD10G28_MODE_PRESET_SD_2G5 */ + .bwidth = 10, + .cmu_sel = SPX5_SD10G28_CMU_AUX2, + .rate = 0x2, + .dfe_enable = 0, + .dfe_tap = 0, + .pi_bw_gen1 = 0x7, + .duty_cycle = 0x0, + }, + { /* SPX5_SD10G28_MODE_PRESET_1000BASEX */ + .bwidth = 10, + .cmu_sel = SPX5_SD10G28_CMU_AUX1, + .rate = 0x3, + .dfe_enable = 0, + .dfe_tap = 0, + .pi_bw_gen1 = 0x7, + .duty_cycle = 0x0, + }, +}; + +/* map from SD25G28 interface width to configuration value */ +static u8 sd25g28_get_iw_setting(struct device *dev, const u8 interface_width) +{ + switch (interface_width) { + case 10: return 0; + case 16: return 1; + case 32: return 3; + case 40: return 4; + case 64: return 5; + default: + dev_err(dev, "%s: Illegal value %d for interface width\n", + __func__, interface_width); + } + return 0; +} + +/* map from SD10G28 interface width to configuration value */ +static u8 sd10g28_get_iw_setting(struct device *dev, const u8 interface_width) +{ + switch (interface_width) { + case 10: return 0; + case 16: return 1; + case 20: return 2; + case 32: return 3; + case 40: return 4; + case 64: return 7; + default: + dev_err(dev, "%s: Illegal value %d for interface width\n", __func__, + interface_width); + return 0; + } +} + +static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro, + struct sparx5_sd25g28_mode_preset *mode) +{ + switch (macro->serdesmode) { + case SPX5_SD_MODE_SFI: + if (macro->speed == SPEED_25000) + *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000]; + else if (macro->speed == SPEED_10000) + *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_10000]; + else if (macro->speed == SPEED_5000) + *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_5000]; + break; + case SPX5_SD_MODE_2G5: + *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_SD_2G5]; + break; + case SPX5_SD_MODE_1000BASEX: + *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_1000BASEX]; + break; + case SPX5_SD_MODE_100FX: + /* Not supported */ + return -EINVAL; + default: + *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000]; + break; + } + return 0; +} + +static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro, + struct sparx5_sd10g28_mode_preset *mode, + struct sparx5_sd10g28_args *args) +{ + switch (macro->serdesmode) { + case SPX5_SD_MODE_SFI: + if (macro->speed == SPEED_10000) { + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000]; + } else if (macro->speed == SPEED_5000) { + if (args->is_6g) + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_6G]; + else + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_10G]; + } else { + dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)", + __func__, macro->speed, macro->sidx, + macro->serdesmode); + return -EINVAL; + } + break; + case SPX5_SD_MODE_QSGMII: + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_QSGMII]; + break; + case SPX5_SD_MODE_2G5: + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SD_2G5]; + break; + case SPX5_SD_MODE_100FX: + case SPX5_SD_MODE_1000BASEX: + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_1000BASEX]; + break; + default: + *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000]; + break; + } + return 0; +} + +static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro, + struct sparx5_sd25g28_media_preset *media, + struct sparx5_sd25g28_mode_preset *mode, + struct sparx5_sd25g28_args *args, + struct sparx5_sd25g28_params *params) +{ + u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth); + struct sparx5_sd25g28_params init = { + .r_d_width_ctrl_2_0 = iw, + .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, + .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, + .cfg_vco_div_mode_1_0 = mode->vco_div_mode, + .cfg_pre_divsel_1_0 = mode->pre_divsel, + .cfg_sel_div_3_0 = mode->sel_div, + .cfg_vco_start_code_3_0 = 0, + .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth, + .cfg_tx_prediv_1_0 = mode->tx_pre_div, + .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth, + .cfg_tx_subrate_2_0 = mode->subrate, + .cfg_rx_subrate_2_0 = mode->subrate, + .r_multi_lane_mode = 0, + .cfg_cdrck_en = 1, + .cfg_dfeck_en = mode->dfe_enable, + .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, + .cfg_dfedmx_pd = 1, + .cfg_dfetap_en_5_1 = mode->dfe_tap, + .cfg_dmux_pd = 0, + .cfg_dmux_clk_pd = 1, + .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, + .cfg_pi_DFE_en = mode->dfe_enable, + .cfg_pi_en = 1, + .cfg_pd_ctle = 0, + .cfg_summer_en = 1, + .cfg_pmad_ck_pd = 0, + .cfg_pd_clk = 0, + .cfg_pd_cml = 0, + .cfg_pd_driver = 0, + .cfg_rx_reg_pu = 1, + .cfg_pd_rms_det = 1, + .cfg_dcdr_pd = 0, + .cfg_ecdr_pd = 1, + .cfg_pd_sq = 1, + .cfg_itx_ipdriver_base_2_0 = mode->txmargin, + .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, + .cfg_tap_main = media->cfg_tap_main, + .cfg_en_main = media->cfg_en_main, + .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, + .cfg_en_adv = media->cfg_en_adv, + .cfg_en_dly = media->cfg_en_dly, + .cfg_iscan_en = 0, + .l1_pcs_en_fast_iscan = 0, + .l0_cfg_bw_1_0 = 0, + .cfg_en_dummy = 0, + .cfg_pll_reserve_3_0 = args->com_pll_reserve, + .l0_cfg_txcal_en = mode->com_txcal_en, + .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb, + .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb, + .cfg_tx_reserve_15_8 = mode->tx_reserve_msb, + .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb, + .cfg_bw_1_0 = mode->bw, + .cfg_txcal_man_en = 1, + .cfg_phase_man_4_0 = 0, + .cfg_quad_man_1_0 = 0, + .cfg_txcal_shift_code_5_0 = 2, + .cfg_txcal_valid_sel_3_0 = 4, + .cfg_txcal_en = 0, + .cfg_cdr_kf_2_0 = 1, + .cfg_cdr_m_7_0 = 6, + .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0, + .cfg_pi_steps_1_0 = 0, + .cfg_dis_2ndorder = 1, + .cfg_ctle_rstn = mode->cfg_ctle_rstn, + .r_dfe_rstn = mode->r_dfe_rstn, + .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0, + .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base, + .cfg_rx_reserve_7_0 = 0xbf, + .cfg_rx_reserve_15_8 = 0x61, + .cfg_rxterm_2_0 = mode->rxterm, + .cfg_fom_selm = 0, + .cfg_rx_sp_ctle_1_0 = 0, + .cfg_isel_ctle_1_0 = 0, + .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0, + .cfg_vga_byp = 1, + .cfg_agc_adpt_byp = 1, + .cfg_eqr_byp = 1, + .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0, + .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0, + .cfg_sum_setcm_en = 1, + .cfg_pi_dfe_en = 1, + .cfg_init_pos_iscan_6_0 = 6, + .cfg_init_pos_ipi_6_0 = 9, + .cfg_dfedig_m_2_0 = 6, + .cfg_en_dfedig = mode->dfe_enable, + .r_d_width_ctrl_from_hwt = 0, + .r_reg_manual = 1, + .reg_rst = args->reg_rst, + .cfg_jc_byp = 1, + .cfg_common_reserve_7_0 = 1, + .cfg_pll_lol_set = 1, + .cfg_tx2rx_lp_en = 0, + .cfg_txlb_en = 0, + .cfg_rx2tx_lp_en = 0, + .cfg_rxlb_en = 0, + .r_tx_pol_inv = args->txinvert, + .r_rx_pol_inv = args->rxinvert, + }; + + *params = init; +} + +static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro, + struct sparx5_sd10g28_media_preset *media, + struct sparx5_sd10g28_mode_preset *mode, + struct sparx5_sd10g28_args *args, + struct sparx5_sd10g28_params *params) +{ + u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth); + struct sparx5_sd10g28_params init = { + .skip_cmu_cfg = args->skip_cmu_cfg, + .is_6g = args->is_6g, + .cmu_sel = mode->cmu_sel, + .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6, + .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2), + .cfg_lane_reserve_15_8 = mode->duty_cycle, + .cfg_txrate_1_0 = mode->rate, + .cfg_rxrate_1_0 = mode->rate, + .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX, + .r_d_width_ctrl_2_0 = iw, + .cfg_pma_tx_ck_bitwidth_2_0 = iw, + .cfg_rxdiv_sel_2_0 = iw, + .r_pcs2pma_phymode_4_0 = 0, + .cfg_lane_id_2_0 = 0, + .cfg_cdrck_en = 1, + .cfg_dfeck_en = mode->dfe_enable, + .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, + .cfg_dfetap_en_5_1 = mode->dfe_tap, + .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, + .cfg_pi_DFE_en = mode->dfe_enable, + .cfg_pi_en = 1, + .cfg_pd_ctle = 0, + .cfg_summer_en = 1, + .cfg_pd_rx_cktree = 0, + .cfg_pd_clk = 0, + .cfg_pd_cml = 0, + .cfg_pd_driver = 0, + .cfg_rx_reg_pu = 1, + .cfg_d_cdr_pd = 0, + .cfg_pd_sq = mode->dfe_enable, + .cfg_rxdet_en = 0, + .cfg_rxdet_str = 0, + .r_multi_lane_mode = 0, + .cfg_en_adv = media->cfg_en_adv, + .cfg_en_main = 1, + .cfg_en_dly = media->cfg_en_dly, + .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, + .cfg_tap_main = media->cfg_tap_main, + .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, + .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0, + .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0, + .cfg_eq_res_3_0 = media->cfg_eq_res_3_0, + .cfg_eq_r_byp = media->cfg_eq_r_byp, + .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0, + .cfg_en_dfedig = mode->dfe_enable, + .cfg_sum_setcm_en = 1, + .cfg_en_preemph = 0, + .cfg_itx_ippreemp_base_1_0 = 0, + .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6), + .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63), + .cfg_txswing_half = (args->txmargin), + .cfg_dis_2nd_order = 0x1, + .cfg_rx_ssc_lh = 0x0, + .cfg_pi_floop_steps_1_0 = 0x0, + .cfg_pi_ext_dac_23_16 = (1 << 5), + .cfg_pi_ext_dac_15_8 = (0 << 6), + .cfg_iscan_ext_dac_7_0 = (1 << 7) + 9, + .cfg_cdr_kf_gen1_2_0 = 1, + .cfg_cdr_kf_gen2_2_0 = 1, + .cfg_cdr_kf_gen3_2_0 = 1, + .cfg_cdr_kf_gen4_2_0 = 1, + .r_cdr_m_gen1_7_0 = 4, + .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1, + .cfg_pi_bw_gen2 = mode->pi_bw_gen1, + .cfg_pi_bw_gen3 = mode->pi_bw_gen1, + .cfg_pi_bw_gen4 = mode->pi_bw_gen1, + .cfg_pi_ext_dac_7_0 = 3, + .cfg_pi_steps = 0, + .cfg_mp_max_3_0 = 1, + .cfg_rstn_dfedig = mode->dfe_enable, + .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0, + .cfg_predrv_slewrate_1_0 = 3, + .cfg_itx_ipcml_base_1_0 = 0, + .cfg_ip_pre_base_1_0 = 0, + .r_cdr_m_gen2_7_0 = 2, + .r_cdr_m_gen3_7_0 = 2, + .r_cdr_m_gen4_7_0 = 2, + .r_en_auto_cdr_rstn = 0, + .cfg_oscal_afe = 1, + .cfg_pd_osdac_afe = 0, + .cfg_resetb_oscal_afe[0] = 0, + .cfg_resetb_oscal_afe[1] = 1, + .cfg_center_spreading = 0, + .cfg_m_cnt_maxval_4_0 = 15, + .cfg_ncnt_maxval_7_0 = 32, + .cfg_ncnt_maxval_10_8 = 6, + .cfg_ssc_en = 1, + .cfg_tx2rx_lp_en = 0, + .cfg_txlb_en = 0, + .cfg_rx2tx_lp_en = 0, + .cfg_rxlb_en = 0, + .r_tx_pol_inv = args->txinvert, + .r_rx_pol_inv = args->rxinvert, + }; + + *params = init; +} + +static void sparx5_sd25g28_reset(void __iomem *regs[], + struct sparx5_sd25g28_params *params, + u32 sd_index) +{ + if (params->reg_rst == 1) { + sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1), + SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, + sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))); + + usleep_range(1000, 2000); + + sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), + SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, + sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))); + } +} + +static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro, + struct sparx5_sd25g28_params *params) +{ + struct sparx5_serdes_private *priv = macro->priv; + void __iomem **regs = priv->regs; + struct device *dev = priv->dev; + u32 sd_index = macro->stpidx; + u32 value; + + sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1), + SD_LANE_25G_SD_LANE_CFG_MACRO_RST, + priv, + SD_LANE_25G_SD_LANE_CFG(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF), + SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, + priv, + SD25G_LANE_CMU_FF(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET + (params->r_d_width_ctrl_from_hwt) | + SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual), + SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT | + SD25G_LANE_CMU_1A_R_REG_MANUAL, + priv, + SD25G_LANE_CMU_1A(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET + (params->cfg_common_reserve_7_0), + SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, + priv, + SD25G_LANE_CMU_31(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy), + SD25G_LANE_CMU_09_CFG_EN_DUMMY, + priv, + SD25G_LANE_CMU_09(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET + (params->cfg_pll_reserve_3_0), + SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, + priv, + SD25G_LANE_CMU_13(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en), + SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, + priv, + SD25G_LANE_CMU_40(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET + (params->l0_cfg_tx_reserve_15_8), + SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, + priv, + SD25G_LANE_CMU_46(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET + (params->l0_cfg_tx_reserve_7_0), + SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, + priv, + SD25G_LANE_CMU_45(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0), + SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, + priv, + SD25G_LANE_CMU_0B(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1), + SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, + priv, + SD25G_LANE_CMU_0B(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0), + SD25G_LANE_CMU_19_R_CK_RESETB, + priv, + SD25G_LANE_CMU_19(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1), + SD25G_LANE_CMU_19_R_CK_RESETB, + priv, + SD25G_LANE_CMU_19(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0), + SD25G_LANE_CMU_18_R_PLL_RSTN, + priv, + SD25G_LANE_CMU_18(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1), + SD25G_LANE_CMU_18_R_PLL_RSTN, + priv, + SD25G_LANE_CMU_18(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0), + SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, + priv, + SD25G_LANE_CMU_1A(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET + (params->r_txfifo_ck_div_pmad_2_0) | + SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET + (params->r_rxfifo_ck_div_pmad_2_0), + SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 | + SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, + priv, + SD25G_LANE_CMU_30(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) | + SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET + (params->cfg_vco_div_mode_1_0), + SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET | + SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, + priv, + SD25G_LANE_CMU_0C(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET + (params->cfg_pre_divsel_1_0), + SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, + priv, + SD25G_LANE_CMU_0D(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0), + SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, + priv, + SD25G_LANE_CMU_0E(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00), + SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, + priv, + SD25G_LANE_CMU_FF(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET + (params->cfg_pma_tx_ck_bitwidth_2_0), + SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, + priv, + SD25G_LANE_LANE_0C(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET + (params->cfg_tx_prediv_1_0), + SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, + priv, + SD25G_LANE_LANE_01(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET + (params->cfg_rxdiv_sel_2_0), + SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, + priv, + SD25G_LANE_LANE_18(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET + (params->cfg_tx_subrate_2_0), + SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, + priv, + SD25G_LANE_LANE_2C(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET + (params->cfg_rx_subrate_2_0), + SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, + priv, + SD25G_LANE_LANE_28(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), + SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, + priv, + SD25G_LANE_LANE_18(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET + (params->cfg_dfetap_en_5_1), + SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, + priv, + SD25G_LANE_LANE_0F(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), + SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, + priv, + SD25G_LANE_LANE_18(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en), + SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, + priv, + SD25G_LANE_LANE_1D(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd), + SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, + priv, + SD25G_LANE_LANE_19(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET + (params->cfg_itx_ipdriver_base_2_0), + SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, + priv, + SD25G_LANE_LANE_01(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0), + SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, + priv, + SD25G_LANE_LANE_03(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0), + SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, + priv, + SD25G_LANE_LANE_06(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) | + SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly), + SD25G_LANE_LANE_07_LN_CFG_EN_ADV | + SD25G_LANE_LANE_07_LN_CFG_EN_DLY, + priv, + SD25G_LANE_LANE_07(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET + (params->cfg_tx_reserve_15_8), + SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, + priv, + SD25G_LANE_LANE_43(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET + (params->cfg_tx_reserve_7_0), + SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, + priv, + SD25G_LANE_LANE_42(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0), + SD25G_LANE_LANE_05_LN_CFG_BW_1_0, + priv, + SD25G_LANE_LANE_05(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET + (params->cfg_txcal_man_en), + SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, + priv, + SD25G_LANE_LANE_0B(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET + (params->cfg_txcal_shift_code_5_0), + SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, + priv, + SD25G_LANE_LANE_0A(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET + (params->cfg_txcal_valid_sel_3_0), + SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, + priv, + SD25G_LANE_LANE_09(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0), + SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, + priv, + SD25G_LANE_LANE_1A(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0), + SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, + priv, + SD25G_LANE_LANE_1B(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0), + SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, + priv, + SD25G_LANE_LANE_2B(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET + (params->cfg_dis_2ndorder), + SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, + priv, + SD25G_LANE_LANE_2C(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn), + SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, + priv, + SD25G_LANE_LANE_2E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET + (params->cfg_itx_ipcml_base_1_0), + SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, + priv, + SD25G_LANE_LANE_00(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET + (params->cfg_rx_reserve_7_0), + SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, + priv, + SD25G_LANE_LANE_44(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET + (params->cfg_rx_reserve_15_8), + SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, + priv, + SD25G_LANE_LANE_45(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) | + SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0), + SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN | + SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, + priv, + SD25G_LANE_LANE_0D(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET + (params->cfg_vga_ctrl_byp_4_0), + SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, + priv, + SD25G_LANE_LANE_21(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET + (params->cfg_eqr_force_3_0), + SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, + priv, + SD25G_LANE_LANE_22(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET + (params->cfg_eqc_force_3_0) | + SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd), + SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 | + SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, + priv, + SD25G_LANE_LANE_1C(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET + (params->cfg_sum_setcm_en), + SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, + priv, + SD25G_LANE_LANE_1E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET + (params->cfg_init_pos_iscan_6_0), + SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, + priv, + SD25G_LANE_LANE_25(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET + (params->cfg_init_pos_ipi_6_0), + SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, + priv, + SD25G_LANE_LANE_26(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), + SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, + priv, + SD25G_LANE_LANE_18(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET + (params->cfg_dfedig_m_2_0), + SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, + priv, + SD25G_LANE_LANE_0E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig), + SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, + priv, + SD25G_LANE_LANE_0E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) | + SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv), + SD25G_LANE_LANE_40_LN_R_TX_POL_INV | + SD25G_LANE_LANE_40_LN_R_RX_POL_INV, + priv, + SD25G_LANE_LANE_40(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) | + SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en), + SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN | + SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, + priv, + SD25G_LANE_LANE_04(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en), + SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, + priv, + SD25G_LANE_LANE_1E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en), + SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, + priv, + SD25G_LANE_LANE_19(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0), + SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, + priv, + SD25G_LANE_LANE_2E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1), + SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, + priv, + SD25G_LANE_LANE_2E(sd_index)); + + sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0), + SD_LANE_25G_SD_LANE_CFG_MACRO_RST, + priv, + SD_LANE_25G_SD_LANE_CFG(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0), + SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, + priv, + SD25G_LANE_LANE_1C(sd_index)); + + usleep_range(1000, 2000); + + sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1), + SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, + priv, + SD25G_LANE_LANE_1C(sd_index)); + + usleep_range(10000, 20000); + + sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff), + SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, + priv, + SD25G_LANE_CMU_FF(sd_index)); + + value = readl(sdx5_addr(regs, SD25G_LANE_CMU_C0(sd_index))); + value = SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(value); + + if (value) { + dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value); + return -EINVAL; + } + + value = readl(sdx5_addr(regs, SD_LANE_25G_SD_LANE_STAT(sd_index))); + value = SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(value); + + if (value != 0x1) { + dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); + return -EINVAL; + } + sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1), + SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, + priv, + SD25G_LANE_CMU_2A(sd_index)); + + sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0), + SD_LANE_25G_SD_SER_RST_SER_RST, + priv, + SD_LANE_25G_SD_SER_RST(sd_index)); + + sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0), + SD_LANE_25G_SD_DES_RST_DES_RST, + priv, + SD_LANE_25G_SD_DES_RST(sd_index)); + + sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0), + SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, + priv, + SD25G_LANE_CMU_FF(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET + (params->cfg_alos_thr_2_0), + SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, + priv, + SD25G_LANE_LANE_2D(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0), + SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, + priv, + SD25G_LANE_LANE_2E(sd_index)); + + sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0), + SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, + priv, + SD25G_LANE_LANE_2E(sd_index)); + + return 0; +} + +static void sparx5_sd10g28_reset(void __iomem *regs[], u32 lane_index) +{ + /* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */ + sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(1), + SD_LANE_SD_LANE_CFG_EXT_CFG_RST, + sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index))); + + usleep_range(1000, 2000); + + sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), + SD_LANE_SD_LANE_CFG_EXT_CFG_RST, + sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index))); +} + +static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro, + struct sparx5_sd10g28_params *params) +{ + struct sparx5_serdes_private *priv = macro->priv; + void __iomem **regs = priv->regs; + struct device *dev = priv->dev; + u32 lane_index = macro->sidx; + u32 sd_index = macro->stpidx; + void __iomem *sd_inst; + u32 value; + + if (params->is_6g) + sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index); + else + sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, sd_index); + + sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1), + SD_LANE_SD_LANE_CFG_MACRO_RST, + priv, + SD_LANE_SD_LANE_CFG(lane_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) | + SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) | + SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) | + SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) | + SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0), + SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT | + SD10G_LANE_LANE_93_R_REG_MANUAL | + SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT | + SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT | + SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, + sd_inst, + SD10G_LANE_LANE_93(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) | + SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) | + SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) | + SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1), + SD10G_LANE_LANE_94_R_ISCAN_REG | + SD10G_LANE_LANE_94_R_TXEQ_REG | + SD10G_LANE_LANE_94_R_MISC_REG | + SD10G_LANE_LANE_94_R_SWING_REG, + sd_inst, + SD10G_LANE_LANE_94(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1), + SD10G_LANE_LANE_9E_R_RXEQ_REG, + sd_inst, + SD10G_LANE_LANE_9E(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) | + SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) | + SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1), + SD10G_LANE_LANE_A1_R_SSC_FROM_HWT | + SD10G_LANE_LANE_A1_R_CDR_FROM_HWT | + SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, + sd_inst, + SD10G_LANE_LANE_A1(sd_index)); + + sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) | + SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel), + SD_LANE_SD_LANE_CFG_RX_REF_SEL | + SD_LANE_SD_LANE_CFG_TX_REF_SEL, + priv, + SD_LANE_SD_LANE_CFG(lane_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET + (params->cfg_lane_reserve_7_0), + SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, + sd_inst, + SD10G_LANE_LANE_40(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET + (params->cfg_ssc_rtl_clk_sel), + SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, + sd_inst, + SD10G_LANE_LANE_50(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET + (params->cfg_txrate_1_0) | + SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET + (params->cfg_rxrate_1_0), + SD10G_LANE_LANE_35_CFG_TXRATE_1_0 | + SD10G_LANE_LANE_35_CFG_RXRATE_1_0, + sd_inst, + SD10G_LANE_LANE_35(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET + (params->r_d_width_ctrl_2_0), + SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, + sd_inst, + SD10G_LANE_LANE_94(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET + (params->cfg_pma_tx_ck_bitwidth_2_0), + SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, + sd_inst, + SD10G_LANE_LANE_01(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET + (params->cfg_rxdiv_sel_2_0), + SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, + sd_inst, + SD10G_LANE_LANE_30(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET + (params->r_pcs2pma_phymode_4_0), + SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, + sd_inst, + SD10G_LANE_LANE_A2(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), + SD10G_LANE_LANE_13_CFG_CDRCK_EN, + sd_inst, + SD10G_LANE_LANE_13(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET + (params->cfg_dfeck_en) | + SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) | + SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET + (params->cfg_erramp_pd), + SD10G_LANE_LANE_23_CFG_DFECK_EN | + SD10G_LANE_LANE_23_CFG_DFE_PD | + SD10G_LANE_LANE_23_CFG_ERRAMP_PD, + sd_inst, + SD10G_LANE_LANE_23(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET + (params->cfg_dfetap_en_5_1), + SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, + sd_inst, + SD10G_LANE_LANE_22(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET + (params->cfg_pi_DFE_en), + SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, + sd_inst, + SD10G_LANE_LANE_1A(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) | + SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) | + SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) | + SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET + (params->cfg_tap_adv_3_0), + SD10G_LANE_LANE_02_CFG_EN_ADV | + SD10G_LANE_LANE_02_CFG_EN_MAIN | + SD10G_LANE_LANE_02_CFG_EN_DLY | + SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, + sd_inst, + SD10G_LANE_LANE_02(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main), + SD10G_LANE_LANE_03_CFG_TAP_MAIN, + sd_inst, + SD10G_LANE_LANE_03(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET + (params->cfg_tap_dly_4_0), + SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, + sd_inst, + SD10G_LANE_LANE_04(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET + (params->cfg_vga_ctrl_3_0), + SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, + sd_inst, + SD10G_LANE_LANE_2F(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET + (params->cfg_vga_cp_2_0), + SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, + sd_inst, + SD10G_LANE_LANE_2F(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET + (params->cfg_eq_res_3_0), + SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, + sd_inst, + SD10G_LANE_LANE_0B(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp), + SD10G_LANE_LANE_0D_CFG_EQR_BYP, + sd_inst, + SD10G_LANE_LANE_0D(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET + (params->cfg_eq_c_force_3_0) | + SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET + (params->cfg_sum_setcm_en), + SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 | + SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, + sd_inst, + SD10G_LANE_LANE_0E(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET + (params->cfg_en_dfedig), + SD10G_LANE_LANE_23_CFG_EN_DFEDIG, + sd_inst, + SD10G_LANE_LANE_23(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET + (params->cfg_en_preemph), + SD10G_LANE_LANE_06_CFG_EN_PREEMPH, + sd_inst, + SD10G_LANE_LANE_06(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET + (params->cfg_itx_ippreemp_base_1_0) | + SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET + (params->cfg_itx_ipdriver_base_2_0), + SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 | + SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, + sd_inst, + SD10G_LANE_LANE_33(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET + (params->cfg_ibias_tune_reserve_5_0), + SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, + sd_inst, + SD10G_LANE_LANE_52(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET + (params->cfg_txswing_half), + SD10G_LANE_LANE_37_CFG_TXSWING_HALF, + sd_inst, + SD10G_LANE_LANE_37(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET + (params->cfg_dis_2nd_order), + SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, + sd_inst, + SD10G_LANE_LANE_3C(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET + (params->cfg_rx_ssc_lh), + SD10G_LANE_LANE_39_CFG_RX_SSC_LH, + sd_inst, + SD10G_LANE_LANE_39(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET + (params->cfg_pi_floop_steps_1_0), + SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, + sd_inst, + SD10G_LANE_LANE_1A(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET + (params->cfg_pi_ext_dac_23_16), + SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, + sd_inst, + SD10G_LANE_LANE_16(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET + (params->cfg_pi_ext_dac_15_8), + SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, + sd_inst, + SD10G_LANE_LANE_15(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET + (params->cfg_iscan_ext_dac_7_0), + SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, + sd_inst, + SD10G_LANE_LANE_26(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET + (params->cfg_cdr_kf_gen1_2_0), + SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, + sd_inst, + SD10G_LANE_LANE_42(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET + (params->r_cdr_m_gen1_7_0), + SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, + sd_inst, + SD10G_LANE_LANE_0F(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET + (params->cfg_pi_bw_gen1_3_0), + SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, + sd_inst, + SD10G_LANE_LANE_24(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET + (params->cfg_pi_ext_dac_7_0), + SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, + sd_inst, + SD10G_LANE_LANE_14(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps), + SD10G_LANE_LANE_1A_CFG_PI_STEPS, + sd_inst, + SD10G_LANE_LANE_1A(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET + (params->cfg_mp_max_3_0), + SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, + sd_inst, + SD10G_LANE_LANE_3A(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET + (params->cfg_rstn_dfedig), + SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, + sd_inst, + SD10G_LANE_LANE_31(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET + (params->cfg_alos_thr_3_0), + SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, + sd_inst, + SD10G_LANE_LANE_48(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET + (params->cfg_predrv_slewrate_1_0), + SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, + sd_inst, + SD10G_LANE_LANE_36(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET + (params->cfg_itx_ipcml_base_1_0), + SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, + sd_inst, + SD10G_LANE_LANE_32(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET + (params->cfg_ip_pre_base_1_0), + SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, + sd_inst, + SD10G_LANE_LANE_37(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET + (params->cfg_lane_reserve_15_8), + SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, + sd_inst, + SD10G_LANE_LANE_41(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET + (params->r_en_auto_cdr_rstn), + SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, + sd_inst, + SD10G_LANE_LANE_9E(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET + (params->cfg_oscal_afe) | + SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET + (params->cfg_pd_osdac_afe), + SD10G_LANE_LANE_0C_CFG_OSCAL_AFE | + SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, + sd_inst, + SD10G_LANE_LANE_0C(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET + (params->cfg_resetb_oscal_afe[0]), + SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, + sd_inst, + SD10G_LANE_LANE_0B(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET + (params->cfg_resetb_oscal_afe[1]), + SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, + sd_inst, + SD10G_LANE_LANE_0B(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET + (params->r_tx_pol_inv) | + SD10G_LANE_LANE_83_R_RX_POL_INV_SET + (params->r_rx_pol_inv), + SD10G_LANE_LANE_83_R_TX_POL_INV | + SD10G_LANE_LANE_83_R_RX_POL_INV, + sd_inst, + SD10G_LANE_LANE_83(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET + (params->cfg_rx2tx_lp_en) | + SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET + (params->cfg_tx2rx_lp_en), + SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN | + SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, + sd_inst, + SD10G_LANE_LANE_06(sd_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) | + SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en), + SD10G_LANE_LANE_0E_CFG_RXLB_EN | + SD10G_LANE_LANE_0E_CFG_TXLB_EN, + sd_inst, + SD10G_LANE_LANE_0E(sd_index)); + + sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0), + SD_LANE_SD_LANE_CFG_MACRO_RST, + priv, + SD_LANE_SD_LANE_CFG(lane_index)); + + sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1), + SD10G_LANE_LANE_50_CFG_SSC_RESETB, + sd_inst, + SD10G_LANE_LANE_50(sd_index)); + + sdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1), + SD10G_LANE_LANE_50_CFG_SSC_RESETB, + priv, + SD10G_LANE_LANE_50(sd_index)); + + sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100), + SD_LANE_MISC_SD_125_RST_DIS, + priv, + SD_LANE_MISC(lane_index)); + + sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100), + SD_LANE_MISC_RX_ENA, + priv, + SD_LANE_MISC(lane_index)); + + sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100), + SD_LANE_MISC_MUX_ENA, + priv, + SD_LANE_MISC(lane_index)); + + usleep_range(3000, 6000); + + value = readl(sdx5_addr(regs, SD_LANE_SD_LANE_STAT(lane_index))); + value = SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(value); + if (value != 1) { + dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); + return -EINVAL; + } + + sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0), + SD_LANE_SD_SER_RST_SER_RST, + priv, + SD_LANE_SD_SER_RST(lane_index)); + + sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0), + SD_LANE_SD_DES_RST_DES_RST, + priv, + SD_LANE_SD_DES_RST(lane_index)); + + return 0; +} + +static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset) +{ + struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media]; + struct sparx5_sd25g28_mode_preset mode; + struct sparx5_sd25g28_args args = { + .rxinvert = 1, + .txinvert = 0, + .txswing = 240, + .com_pll_reserve = 0xf, + .reg_rst = reset, + }; + struct sparx5_sd25g28_params params; + int err; + + err = sparx5_sd10g25_get_mode_preset(macro, &mode); + if (err) + return err; + sparx5_sd25g28_get_params(macro, &media, &mode, &args, ¶ms); + sparx5_sd25g28_reset(macro->priv->regs, ¶ms, macro->stpidx); + return sparx5_sd25g28_apply_params(macro, ¶ms); +} + +static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset) +{ + struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media]; + struct sparx5_sd10g28_mode_preset mode; + struct sparx5_sd10g28_params params; + struct sparx5_sd10g28_args args = { + .is_6g = (macro->serdestype == SPX5_SDT_6G), + .txinvert = 0, + .rxinvert = 1, + .txswing = 240, + .reg_rst = reset, + }; + int err; + + err = sparx5_sd10g28_get_mode_preset(macro, &mode, &args); + if (err) + return err; + sparx5_sd10g28_get_params(macro, &media, &mode, &args, ¶ms); + sparx5_sd10g28_reset(macro->priv->regs, macro->sidx); + return sparx5_sd10g28_apply_params(macro, ¶ms); +} + +/* Power down serdes TX driver */ +static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn) +{ + struct sparx5_serdes_private *priv = macro->priv; + void __iomem *sd_inst; + + if (macro->serdestype == SPX5_SDT_6G) + sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx); + else if (macro->serdestype == SPX5_SDT_10G) + sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, macro->stpidx); + else + sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx); + + if (macro->serdestype == SPX5_SDT_25G) { + sdx5_inst_rmw(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(pwdn), + SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, + sd_inst, + SD25G_LANE_LANE_04(0)); + } else { + /* 6G and 10G */ + sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(pwdn), + SD10G_LANE_LANE_06_CFG_PD_DRIVER, + sd_inst, + SD10G_LANE_LANE_06(0)); + } + return 0; +} + +static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro) +{ + struct sparx5_serdes_private *priv = macro->priv; + + if (macro->serdesmode == SPX5_SD_MODE_100FX) { + u32 freq = priv->coreclock == 250000000 ? 2 : + priv->coreclock == 500000000 ? 1 : 0; + + sdx5_rmw(SD_LANE_MISC_CORE_CLK_FREQ_SET(freq), + SD_LANE_MISC_CORE_CLK_FREQ, + priv, + SD_LANE_MISC(macro->sidx)); + } + return 0; +} + +static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv, + u32 cmu_idx, + void __iomem *cmu_tgt, + void __iomem *cmu_cfg_tgt, + u32 spd10g) +{ + void __iomem **regs = priv->regs; + struct device *dev = priv->dev; + int value; + + cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); + cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); + + if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || + cmu_idx == 10 || cmu_idx == 13) { + spd10g = 0; + } + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1), + SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), + SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1), + SD_CMU_CFG_SD_CMU_CFG_CMU_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | + SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), + SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT | + SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT | + SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT | + SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT | + SD_CMU_CMU_45_R_EN_RATECHG_CTRL, + cmu_tgt, + SD_CMU_CMU_45(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), + SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, + cmu_tgt, + SD_CMU_CMU_47(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), + SD_CMU_CMU_1B_CFG_RESERVE_7_0, + cmu_tgt, + SD_CMU_CMU_1B(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), + SD_CMU_CMU_0D_CFG_JC_BYP, + cmu_tgt, + SD_CMU_CMU_0D(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1), + SD_CMU_CMU_1F_CFG_VTUNE_SEL, + cmu_tgt, + SD_CMU_CMU_1F(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3), + SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, + cmu_tgt, + SD_CMU_CMU_00(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3), + SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, + cmu_tgt, + SD_CMU_CMU_05(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1), + SD_CMU_CMU_30_R_PLL_DLOL_EN, + cmu_tgt, + SD_CMU_CMU_30(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g), + SD_CMU_CMU_09_CFG_SW_10G, + cmu_tgt, + SD_CMU_CMU_09(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), + SD_CMU_CFG_SD_CMU_CFG_CMU_RST, + cmu_cfg_tgt, + SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); + + msleep(20); + + sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), + SD_CMU_CMU_44_R_PLL_RSTN, + cmu_tgt, + SD_CMU_CMU_44(cmu_idx)); + + sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1), + SD_CMU_CMU_44_R_PLL_RSTN, + cmu_tgt, + SD_CMU_CMU_44(cmu_idx)); + + msleep(20); + + value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx))); + value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value); + + if (value) { + dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); + return -EINVAL; + } + sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), + SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, + cmu_tgt, + SD_CMU_CMU_0D(cmu_idx)); + return 0; +} + +static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx) +{ + void __iomem *cmu_tgt, *cmu_cfg_tgt; + u32 spd10g = 1; + + if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || + cmu_idx == 10 || cmu_idx == 13) { + spd10g = 0; + } + + cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); + cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); + + return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g); +} + +static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv) +{ + int idx, err = 0; + + if (!priv->cmu_enabled) { + for (idx = 0; idx < SPX5_CMU_MAX; idx++) { + err = sparx5_cmu_cfg(priv, idx); + if (err) { + dev_err(priv->dev, "CMU %u, error: %d\n", idx, err); + goto leave; + } + } + priv->cmu_enabled = true; + } +leave: + return err; +} + +static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed) +{ + switch (portmode) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + if (speed == SPEED_2500) + return SPX5_SD_MODE_2G5; + if (speed == SPEED_100) + return SPX5_SD_MODE_100FX; + return SPX5_SD_MODE_1000BASEX; + case PHY_INTERFACE_MODE_SGMII: + /* The same Serdes mode is used for both SGMII and 1000BaseX */ + return SPX5_SD_MODE_1000BASEX; + case PHY_INTERFACE_MODE_QSGMII: + return SPX5_SD_MODE_QSGMII; + case PHY_INTERFACE_MODE_10GBASER: + return SPX5_SD_MODE_SFI; + default: + return -EINVAL; + } +} + +static int sparx5_serdes_config(struct sparx5_serdes_macro *macro) +{ + struct device *dev = macro->priv->dev; + int serdesmode; + int err; + + err = sparx5_serdes_cmu_enable(macro->priv); + if (err) + return err; + + serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed); + if (serdesmode < 0) { + dev_err(dev, "SerDes %u, interface not supported: %s\n", + macro->sidx, + phy_modes(macro->portmode)); + return serdesmode; + } + macro->serdesmode = serdesmode; + + sparx5_serdes_clock_config(macro); + + if (macro->serdestype == SPX5_SDT_25G) + err = sparx5_sd25g28_config(macro, false); + else + err = sparx5_sd10g28_config(macro, false); + if (err) { + dev_err(dev, "SerDes %u, config error: %d\n", + macro->sidx, err); + } + return err; +} + +static int sparx5_serdes_power_on(struct phy *phy) +{ + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + + return sparx5_serdes_power_save(macro, false); +} + +static int sparx5_serdes_power_off(struct phy *phy) +{ + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + + return sparx5_serdes_power_save(macro, true); +} + +static int sparx5_serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct sparx5_serdes_macro *macro; + + if (mode != PHY_MODE_ETHERNET) + return -EINVAL; + + switch (submode) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_10GBASER: + macro = phy_get_drvdata(phy); + macro->portmode = submode; + sparx5_serdes_config(macro); + return 0; + default: + return -EINVAL; + } +} + +static int sparx5_serdes_set_media(struct phy *phy, enum phy_media media) +{ + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + + if (media != macro->media) { + macro->media = media; + if (macro->serdesmode != SPX5_SD_MODE_NONE) + sparx5_serdes_config(macro); + } + return 0; +} + +static int sparx5_serdes_set_speed(struct phy *phy, int speed) +{ + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + + if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) + return -EINVAL; + if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) + return -EINVAL; + if (speed != macro->speed) { + macro->speed = speed; + if (macro->serdesmode != SPX5_SD_MODE_NONE) + sparx5_serdes_config(macro); + } + return 0; +} + +static int sparx5_serdes_reset(struct phy *phy) +{ + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + int err; + + err = sparx5_serdes_cmu_enable(macro->priv); + if (err) + return err; + if (macro->serdestype == SPX5_SDT_25G) + err = sparx5_sd25g28_config(macro, true); + else + err = sparx5_sd10g28_config(macro, true); + if (err) { + dev_err(&phy->dev, "SerDes %u, reset error: %d\n", + macro->sidx, err); + } + return err; +} + +static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode, + int submode, + union phy_configure_opts *opts) +{ + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + + if (mode != PHY_MODE_ETHERNET) + return -EINVAL; + + if (macro->speed == 0) + return -EINVAL; + + if (macro->sidx < SPX5_SERDES_10G_START && macro->speed > SPEED_5000) + return -EINVAL; + if (macro->sidx < SPX5_SERDES_25G_START && macro->speed > SPEED_10000) + return -EINVAL; + + switch (submode) { + case PHY_INTERFACE_MODE_1000BASEX: + if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ + macro->speed != SPEED_1000) + return -EINVAL; + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_QSGMII: + if (macro->speed >= SPEED_5000) + return -EINVAL; + break; + case PHY_INTERFACE_MODE_10GBASER: + if (macro->speed < SPEED_5000) + return -EINVAL; + break; + default: + return -EINVAL; + } + return 0; +} + +static const struct phy_ops sparx5_serdes_ops = { + .power_on = sparx5_serdes_power_on, + .power_off = sparx5_serdes_power_off, + .set_mode = sparx5_serdes_set_mode, + .set_media = sparx5_serdes_set_media, + .set_speed = sparx5_serdes_set_speed, + .reset = sparx5_serdes_reset, + .validate = sparx5_serdes_validate, + .owner = THIS_MODULE, +}; + +static int sparx5_phy_create(struct sparx5_serdes_private *priv, + int idx, struct phy **phy) +{ + struct sparx5_serdes_macro *macro; + + *phy = devm_phy_create(priv->dev, NULL, &sparx5_serdes_ops); + if (IS_ERR(*phy)) + return PTR_ERR(*phy); + + macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL); + if (!macro) + return -ENOMEM; + + macro->sidx = idx; + macro->priv = priv; + macro->speed = SPEED_UNKNOWN; + if (idx < SPX5_SERDES_10G_START) { + macro->serdestype = SPX5_SDT_6G; + macro->stpidx = macro->sidx; + } else if (idx < SPX5_SERDES_25G_START) { + macro->serdestype = SPX5_SDT_10G; + macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; + } else { + macro->serdestype = SPX5_SDT_25G; + macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; + } + + phy_set_drvdata(*phy, macro); + + return 0; +} + +static struct sparx5_serdes_io_resource sparx5_serdes_iomap[] = { + { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */ + { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */ + { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */ + { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */ + { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */ + { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */ + { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */ + { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */ + { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */ + { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */ + { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */ + { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */ + { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */ + { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */ + { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */ + { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */ + { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */ + { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */ + { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */ + { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */ + { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */ + { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */ + { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */ + { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */ + { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */ + { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */ + { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */ + { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */ + { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */ + { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */ + { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */ + { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */ + { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */ + { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */ + { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */ + { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */ + { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */ + { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */ + { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */ + { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */ + { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */ + { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */ + { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */ + { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */ + { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */ + { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */ + { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */ + { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */ + { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */ + { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */ + { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */ + { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */ + { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */ + { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */ + { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */ + { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */ + { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */ + { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */ + { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */ + { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */ + { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */ + { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */ + { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */ + { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */ + { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */ + { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */ + { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */ + { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */ + { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */ + { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */ + { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */ + { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */ + { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */ + { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */ + { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */ + { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */ + { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */ + { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */ + { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */ + { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */ + { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */ + { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */ + { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */ + { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */ + { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */ + { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */ + { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */ + { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */ + { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */ + { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */ + { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */ + { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */ + { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */ + { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ +}; + +/* Client lookup function, uses serdes index */ +static struct phy *sparx5_serdes_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct sparx5_serdes_private *priv = dev_get_drvdata(dev); + int idx; + unsigned int sidx; + + if (args->args_count != 1) + return ERR_PTR(-EINVAL); + + sidx = args->args[0]; + + /* Check validity: ERR_PTR(-ENODEV) if not valid */ + for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { + struct sparx5_serdes_macro *macro = + phy_get_drvdata(priv->phys[idx]); + + if (sidx != macro->sidx) + continue; + + return priv->phys[idx]; + } + return ERR_PTR(-ENODEV); +} + +static int sparx5_serdes_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct sparx5_serdes_private *priv; + struct phy_provider *provider; + struct resource *iores; + void __iomem *iomem; + unsigned long clock; + struct clk *clk; + int idx; + int err; + + if (!np && !pdev->dev.platform_data) + return -ENODEV; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + priv->dev = &pdev->dev; + + /* Get coreclock */ + clk = devm_clk_get(priv->dev, NULL); + if (IS_ERR(clk)) { + dev_err(priv->dev, "Failed to get coreclock\n"); + return PTR_ERR(clk); + } + clock = clk_get_rate(clk); + if (clock == 0) { + dev_err(priv->dev, "Invalid coreclock %lu\n", clock); + return -EINVAL; + } + priv->coreclock = clock; + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); + if (IS_ERR(iomem)) { + dev_err(priv->dev, "Unable to get serdes registers: %s\n", + iores->name); + return PTR_ERR(iomem); + } + for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) { + struct sparx5_serdes_io_resource *iomap = &sparx5_serdes_iomap[idx]; + + priv->regs[iomap->id] = iomem + iomap->offset; + } + for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { + err = sparx5_phy_create(priv, idx, &priv->phys[idx]); + if (err) + return err; + } + + provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id sparx5_serdes_match[] = { + { .compatible = "microchip,sparx5-serdes" }, + { } +}; +MODULE_DEVICE_TABLE(of, sparx5_serdes_match); + +static struct platform_driver sparx5_serdes_driver = { + .probe = sparx5_serdes_probe, + .driver = { + .name = "sparx5-serdes", + .of_match_table = sparx5_serdes_match, + }, +}; + +module_platform_driver(sparx5_serdes_driver); + +MODULE_DESCRIPTION("Microchip Sparx5 switch serdes driver"); +MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/microchip/sparx5_serdes.h b/drivers/phy/microchip/sparx5_serdes.h new file mode 100644 index 000000000000..0a3e496e6210 --- /dev/null +++ b/drivers/phy/microchip/sparx5_serdes.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Microchip Sparx5 SerDes driver + * + * Copyright (c) 2020 Microchip Technology Inc. + */ + +#ifndef _SPARX5_SERDES_H_ +#define _SPARX5_SERDES_H_ + +#include "sparx5_serdes_regs.h" + +#define SPX5_SERDES_MAX 33 + +enum sparx5_serdes_type { + SPX5_SDT_6G = 6, + SPX5_SDT_10G = 10, + SPX5_SDT_25G = 25, +}; + +enum sparx5_serdes_mode { + SPX5_SD_MODE_NONE, + SPX5_SD_MODE_2G5, + SPX5_SD_MODE_QSGMII, + SPX5_SD_MODE_100FX, + SPX5_SD_MODE_1000BASEX, + SPX5_SD_MODE_SFI, +}; + +struct sparx5_serdes_private { + struct device *dev; + void __iomem *regs[NUM_TARGETS]; + struct phy *phys[SPX5_SERDES_MAX]; + bool cmu_enabled; + unsigned long coreclock; +}; + +struct sparx5_serdes_macro { + struct sparx5_serdes_private *priv; + u32 sidx; + u32 stpidx; + enum sparx5_serdes_type serdestype; + enum sparx5_serdes_mode serdesmode; + phy_interface_t portmode; + int speed; + enum phy_media media; +}; + +/* Read, Write and modify registers content. + * The register definition macros start at the id + */ +static inline void __iomem *sdx5_addr(void __iomem *base[], + int id, int tinst, int tcnt, + int gbase, int ginst, + int gcnt, int gwidth, + int raddr, int rinst, + int rcnt, int rwidth) +{ + WARN_ON((tinst) >= tcnt); + WARN_ON((ginst) >= gcnt); + WARN_ON((rinst) >= rcnt); + return base[id + (tinst)] + + gbase + ((ginst) * gwidth) + + raddr + ((rinst) * rwidth); +} + +static inline void __iomem *sdx5_inst_baseaddr(void __iomem *base, + int gbase, int ginst, + int gcnt, int gwidth, + int raddr, int rinst, + int rcnt, int rwidth) +{ + WARN_ON((ginst) >= gcnt); + WARN_ON((rinst) >= rcnt); + return base + + gbase + ((ginst) * gwidth) + + raddr + ((rinst) * rwidth); +} + +static inline void sdx5_rmw(u32 val, u32 mask, struct sparx5_serdes_private *priv, + int id, int tinst, int tcnt, + int gbase, int ginst, int gcnt, int gwidth, + int raddr, int rinst, int rcnt, int rwidth) +{ + u32 nval; + void __iomem *addr = + sdx5_addr(priv->regs, id, tinst, tcnt, + gbase, ginst, gcnt, gwidth, + raddr, rinst, rcnt, rwidth); + nval = readl(addr); + nval = (nval & ~mask) | (val & mask); + writel(nval, addr); +} + +static inline void sdx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, + int id, int tinst, int tcnt, + int gbase, int ginst, int gcnt, int gwidth, + int raddr, int rinst, int rcnt, int rwidth) +{ + u32 nval; + void __iomem *addr = + sdx5_inst_baseaddr(iomem, + gbase, ginst, gcnt, gwidth, + raddr, rinst, rcnt, rwidth); + nval = readl(addr); + nval = (nval & ~mask) | (val & mask); + writel(nval, addr); +} + +static inline void sdx5_rmw_addr(u32 val, u32 mask, void __iomem *addr) +{ + u32 nval; + + nval = readl(addr); + nval = (nval & ~mask) | (val & mask); + writel(nval, addr); +} + +static inline void __iomem *sdx5_inst_get(struct sparx5_serdes_private *priv, + int id, int tinst) +{ + return priv->regs[id + tinst]; +} + +static inline void __iomem *sdx5_inst_addr(void __iomem *iomem, + int id, int tinst, int tcnt, + int gbase, + int ginst, int gcnt, int gwidth, + int raddr, + int rinst, int rcnt, int rwidth) +{ + return sdx5_inst_baseaddr(iomem, gbase, ginst, gcnt, gwidth, + raddr, rinst, rcnt, rwidth); +} + + +#endif /* _SPARX5_SERDES_REGS_H_ */ diff --git a/drivers/phy/microchip/sparx5_serdes_regs.h b/drivers/phy/microchip/sparx5_serdes_regs.h new file mode 100644 index 000000000000..b96386a4df5a --- /dev/null +++ b/drivers/phy/microchip/sparx5_serdes_regs.h @@ -0,0 +1,2695 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Microchip Sparx5 SerDes driver + * + * Copyright (c) 2020 Microchip Technology Inc. + */ + +/* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100. + * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f + */ + +#ifndef _SPARX5_SERDES_REGS_H_ +#define _SPARX5_SERDES_REGS_H_ + +#include <linux/bitfield.h> +#include <linux/types.h> +#include <linux/bug.h> + +enum sparx5_serdes_target { + TARGET_SD10G_LANE = 200, + TARGET_SD25G_LANE = 212, + TARGET_SD6G_LANE = 233, + TARGET_SD_CMU = 248, + TARGET_SD_CMU_CFG = 262, + TARGET_SD_LANE = 276, + TARGET_SD_LANE_25G = 301, + NUM_TARGETS = 332 +}; + +#define __REG(...) __VA_ARGS__ + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ +#define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4) + +#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) +#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x) +#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x) + +#define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4) +#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x) +#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x) + +#define SD10G_LANE_LANE_01_CFG_RXDET_STR BIT(5) +#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) +#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ +#define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4) + +#define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0) +#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x) +#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x) + +#define SD10G_LANE_LANE_02_CFG_EN_MAIN BIT(1) +#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x) +#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x) + +#define SD10G_LANE_LANE_02_CFG_EN_DLY BIT(2) +#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x) +#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x) + +#define SD10G_LANE_LANE_02_CFG_EN_DLY2 BIT(3) +#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x) +#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x) + +#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4) +#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x) +#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ +#define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4) + +#define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0) +#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x) +#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ +#define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4) + +#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0) +#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x) +#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ +#define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4) + +#define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0) +#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x) +#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x) + +#define SD10G_LANE_LANE_06_CFG_PD_CLK BIT(1) +#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x) +#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x) + +#define SD10G_LANE_LANE_06_CFG_PD_CML BIT(2) +#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x) +#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x) + +#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN BIT(3) +#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x) +#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x) + +#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4) +#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x) +#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x) + +#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH BIT(5) +#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x) +#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ +#define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4) + +#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0) +#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x) +#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x) + +#define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4) +#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x) +#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x) + +#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN BIT(5) +#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x) +#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x) + +#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE BIT(6) +#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x) +#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x) + +#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ BIT(7) +#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x) +#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ +#define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4) + +#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0) +#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x) +#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x) + +#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ BIT(1) +#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x) +#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x) + +#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE BIT(2) +#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x) +#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x) + +#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ BIT(3) +#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x) +#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x) + +#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4) +#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x) +#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x) + +#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ BIT(5) +#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x) +#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x) + +#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS BIT(6) +#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x) +#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x) + +#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12 BIT(7) +#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x) +#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ +#define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4) + +#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0) +#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x) +#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x) + +#define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4) +#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x) +#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ +#define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4) + +#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0) +#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x) +#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x) + +#define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4) +#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x) +#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x) + +#define SD10G_LANE_LANE_0E_CFG_TXLB_EN BIT(5) +#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x) +#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x) + +#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN BIT(6) +#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x) +#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ +#define SD10G_LANE_LANE_0F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4) + +#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0) +#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x) +#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ +#define SD10G_LANE_LANE_13(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4) + +#define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0) +#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x) +#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x) + +#define SD10G_LANE_LANE_13_CFG_PHID_1T BIT(1) +#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x) +#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x) + +#define SD10G_LANE_LANE_13_CFG_CDRCK_EN BIT(2) +#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x) +#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ +#define SD10G_LANE_LANE_14(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4) + +#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0) +#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x) +#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ +#define SD10G_LANE_LANE_15(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4) + +#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0) +#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x) +#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ +#define SD10G_LANE_LANE_16(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4) + +#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0) +#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x) +#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ +#define SD10G_LANE_LANE_1A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4) + +#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0) +#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x) +#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x) + +#define SD10G_LANE_LANE_1A_CFG_PI_EN BIT(1) +#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x) +#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x) + +#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN BIT(2) +#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x) +#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x) + +#define SD10G_LANE_LANE_1A_CFG_PI_STEPS BIT(3) +#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x) +#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x) + +#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4) +#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x) +#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ +#define SD10G_LANE_LANE_22(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4) + +#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0) +#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x) +#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ +#define SD10G_LANE_LANE_23(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4) + +#define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0) +#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x) +#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x) + +#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG BIT(1) +#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x) +#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x) + +#define SD10G_LANE_LANE_23_CFG_DFECK_EN BIT(2) +#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x) +#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x) + +#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD BIT(3) +#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x) +#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x) + +#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4) +#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x) +#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ +#define SD10G_LANE_LANE_24(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4) + +#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0) +#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x) +#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x) + +#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4) +#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x) +#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ +#define SD10G_LANE_LANE_26(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4) + +#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0) +#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x) +#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ +#define SD10G_LANE_LANE_2F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4) + +#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0) +#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x) +#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x) + +#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4) +#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x) +#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ +#define SD10G_LANE_LANE_30(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4) + +#define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0) +#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x) +#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x) + +#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4) +#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x) +#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ +#define SD10G_LANE_LANE_31(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4) + +#define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0) +#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x) +#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x) + +#define SD10G_LANE_LANE_31_CFG_CDR_RSTN BIT(1) +#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x) +#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x) + +#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG BIT(2) +#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x) +#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x) + +#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN BIT(3) +#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x) +#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x) + +#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4) +#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x) +#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x) + +#define SD10G_LANE_LANE_31_CFG_R50_EN BIT(5) +#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x) +#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ +#define SD10G_LANE_LANE_32(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4) + +#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0) +#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x) +#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x) + +#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4) +#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x) +#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ +#define SD10G_LANE_LANE_33(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4) + +#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) +#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x) +#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x) + +#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4) +#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x) +#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ +#define SD10G_LANE_LANE_35(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4) + +#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0) +#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x) +#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x) + +#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4) +#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x) +#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ +#define SD10G_LANE_LANE_36(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4) + +#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0) +#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x) +#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x) + +#define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4) +#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x) +#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x) + +#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH BIT(5) +#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x) +#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x) + +#define SD10G_LANE_LANE_36_CFG_PRBS_SEL BIT(6) +#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x) +#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x) + +#define SD10G_LANE_LANE_36_CFG_PRBS_SETB BIT(7) +#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x) +#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ +#define SD10G_LANE_LANE_37(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4) + +#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0) +#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x) +#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x) + +#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE BIT(1) +#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x) +#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x) + +#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF BIT(2) +#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x) +#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x) + +#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4) +#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x) +#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ +#define SD10G_LANE_LANE_39(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4) + +#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0) +#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x) +#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x) + +#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4) +#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x) +#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ +#define SD10G_LANE_LANE_3A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4) + +#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0) +#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x) +#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x) + +#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4) +#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x) +#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ +#define SD10G_LANE_LANE_3C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4) + +#define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0) +#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x) +#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x) + +#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER BIT(1) +#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x) +#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ +#define SD10G_LANE_LANE_40(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4) + +#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0) +#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x) +#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ +#define SD10G_LANE_LANE_41(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4) + +#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0) +#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x) +#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x) + +/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ +#define SD10G_LANE_LANE_42(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4) + +#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0) +#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x) +#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x) + +#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4) +#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x) +#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ +#define SD10G_LANE_LANE_48(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4) + +#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0) +#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x) +#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x) + +#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4) +#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x) +#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x) + +#define SD10G_LANE_LANE_48_CFG_CLK_ENQ BIT(5) +#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x) +#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x) + +/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ +#define SD10G_LANE_LANE_50(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4) + +#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0) +#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x) +#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x) + +#define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4) +#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x) +#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x) + +#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL BIT(5) +#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x) +#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x) + +#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL BIT(6) +#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x) +#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x) + +#define SD10G_LANE_LANE_50_CFG_JT_EN BIT(7) +#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x) +#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ +#define SD10G_LANE_LANE_52(t) __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4) + +#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0) +#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x) +#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ +#define SD10G_LANE_LANE_83(t) __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4) + +#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0) +#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x) +#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x) + +#define SD10G_LANE_LANE_83_R_TX_POL_INV BIT(1) +#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x) +#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x) + +#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE BIT(2) +#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x) +#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x) + +#define SD10G_LANE_LANE_83_R_RX_POL_INV BIT(3) +#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x) +#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x) + +#define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4) +#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x) +#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x) + +#define SD10G_LANE_LANE_83_R_CDR_RSTN BIT(5) +#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x) +#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x) + +#define SD10G_LANE_LANE_83_R_CTLE_RSTN BIT(6) +#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x) +#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ +#define SD10G_LANE_LANE_93(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4) + +#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0) +#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x) +#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x) + +#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1) +#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x) +#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x) + +#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE BIT(2) +#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x) +#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x) + +#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL BIT(3) +#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x) +#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x) + +#define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4) +#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x) +#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x) + +#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT BIT(5) +#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x) +#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x) + +#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT BIT(6) +#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x) +#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x) + +#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7) +#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x) +#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x) + +/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ +#define SD10G_LANE_LANE_94(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4) + +#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0) +#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x) +#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x) + +#define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4) +#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x) +#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x) + +#define SD10G_LANE_LANE_94_R_TXEQ_REG BIT(5) +#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x) +#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x) + +#define SD10G_LANE_LANE_94_R_MISC_REG BIT(6) +#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x) +#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x) + +#define SD10G_LANE_LANE_94_R_SWING_REG BIT(7) +#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x) +#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x) + +/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ +#define SD10G_LANE_LANE_9E(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4) + +#define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0) +#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x) +#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x) + +#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1) +#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x) +#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x) + +#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN BIT(2) +#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x) +#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x) + +/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ +#define SD10G_LANE_LANE_A1(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4) + +#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0) +#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x) +#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x) + +#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4) +#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x) +#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x) + +#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT BIT(5) +#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x) +#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x) + +#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6) +#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x) +#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x) + +#define SD10G_LANE_LANE_A1_R_PCLK_GATING BIT(7) +#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x) +#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x) + +/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ +#define SD10G_LANE_LANE_A2(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4) + +#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) +#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x) +#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x) + +/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ +#define SD10G_LANE_LANE_DF(t) __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4) + +#define SD10G_LANE_LANE_DF_LOL_UDL BIT(0) +#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x) +#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x) + +#define SD10G_LANE_LANE_DF_LOL BIT(1) +#define SD10G_LANE_LANE_DF_LOL_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x) +#define SD10G_LANE_LANE_DF_LOL_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_DF_LOL, x) + +#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2) +#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x) +#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x) + +#define SD10G_LANE_LANE_DF_SQUELCH BIT(3) +#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\ + FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x) +#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_09 */ +#define SD25G_LANE_CMU_09(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) + +#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0) +#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x) +#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x) + +#define SD25G_LANE_CMU_09_CFG_EN_DUMMY BIT(1) +#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x) +#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x) + +#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET BIT(2) +#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x) +#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x) + +#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD BIT(3) +#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x) +#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x) + +#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4) +#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x) +#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_0B */ +#define SD25G_LANE_CMU_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) + +#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0) +#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x) +#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x) + +#define SD25G_LANE_CMU_0B_CFG_DISLOL BIT(1) +#define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x) +#define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x) + +#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2) +#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x) +#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x) + +#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN BIT(3) +#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x) +#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x) + +#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD BIT(4) +#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x) +#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x) + +#define SD25G_LANE_CMU_0B_CFG_DISLOS BIT(5) +#define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x) +#define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x) + +#define SD25G_LANE_CMU_0B_CFG_DCLOL BIT(6) +#define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x) +#define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x) + +#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN BIT(7) +#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x) +#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_0C */ +#define SD25G_LANE_CMU_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) + +#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0) +#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x) +#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x) + +#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN BIT(1) +#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x) +#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x) + +#define SD25G_LANE_CMU_0C_CFG_VCO_PD BIT(2) +#define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x) +#define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x) + +#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP BIT(3) +#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x) +#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x) + +#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0 GENMASK(5, 4) +#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x) +#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_0D */ +#define SD25G_LANE_CMU_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) + +#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0) +#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x) +#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x) + +#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN BIT(1) +#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x) +#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x) + +#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP BIT(2) +#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x) +#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x) + +#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP BIT(3) +#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x) +#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x) + +#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0 GENMASK(5, 4) +#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x) +#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_0E */ +#define SD25G_LANE_CMU_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) + +#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0) +#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x) +#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x) + +#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD BIT(4) +#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x) +#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_13 */ +#define SD25G_LANE_CMU_13(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) + +#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0) +#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x) +#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x) + +#define SD25G_LANE_CMU_13_CFG_JT_EN BIT(4) +#define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x) +#define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_18 */ +#define SD25G_LANE_CMU_18(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) + +#define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0) +#define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x) +#define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x) + +#define SD25G_LANE_CMU_18_R_PLL_LOL_SET BIT(1) +#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x) +#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x) + +#define SD25G_LANE_CMU_18_R_PLL_LOS_SET BIT(2) +#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x) +#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x) + +#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0 GENMASK(5, 4) +#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x) +#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_19 */ +#define SD25G_LANE_CMU_19(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) + +#define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0) +#define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x) +#define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x) + +#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN BIT(1) +#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x) +#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x) + +/* SD25G_TARGET:CMU_GRP_0:CMU_1A */ +#define SD25G_LANE_CMU_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) + +#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0) +#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x) +#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x) + +#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT BIT(4) +#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x) +#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x) + +#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE BIT(5) +#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x) +#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x) + +#define SD25G_LANE_CMU_1A_R_REG_MANUAL BIT(6) +#define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x) +#define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x) + +/* SD25G_TARGET:CMU_GRP_1:CMU_2A */ +#define SD25G_LANE_CMU_2A(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) + +#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0) +#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x) +#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x) + +#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE BIT(4) +#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x) +#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x) + +#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS BIT(5) +#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x) +#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x) + +/* SD25G_TARGET:CMU_GRP_1:CMU_30 */ +#define SD25G_LANE_CMU_30(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) + +#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0) +#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x) +#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x) + +#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4) +#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x) +#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x) + +/* SD25G_TARGET:CMU_GRP_1:CMU_31 */ +#define SD25G_LANE_CMU_31(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) + +#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0) +#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x) +#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x) + +/* SD25G_TARGET:CMU_GRP_2:CMU_40 */ +#define SD25G_LANE_CMU_40(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) + +#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0) +#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x) +#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x) + +#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD BIT(1) +#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x) +#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x) + +#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK BIT(2) +#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x) +#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x) + +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN BIT(3) +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x) +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x) + +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN BIT(4) +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x) +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x) + +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST BIT(5) +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x) +#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x) + +/* SD25G_TARGET:CMU_GRP_2:CMU_45 */ +#define SD25G_LANE_CMU_45(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) + +#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0) +#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x) +#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x) + +/* SD25G_TARGET:CMU_GRP_2:CMU_46 */ +#define SD25G_LANE_CMU_46(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) + +#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0) +#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x) +#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x) + +/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ +#define SD25G_LANE_CMU_C0(t) __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) + +#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) +#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x) +#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x) + +#define SD25G_LANE_CMU_C0_PLL_LOL_UDL BIT(4) +#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x) +#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x) + +/* SD25G_TARGET:CMU_GRP_4:CMU_FF */ +#define SD25G_LANE_CMU_FF(t) __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) + +#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0) +#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ + FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x) +#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_00 */ +#define SD25G_LANE_LANE_00(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) + +#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0) +#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x) +#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x) + +#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4) +#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x) +#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_01 */ +#define SD25G_LANE_LANE_01(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) + +#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) +#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x) +#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x) + +#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0 GENMASK(5, 4) +#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x) +#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_03 */ +#define SD25G_LANE_LANE_03(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) + +#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0) +#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x) +#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_04 */ +#define SD25G_LANE_LANE_04(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) + +#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0) +#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x) +#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x) + +#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN BIT(1) +#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x) +#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x) + +#define SD25G_LANE_LANE_04_LN_CFG_PD_CML BIT(2) +#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x) +#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x) + +#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK BIT(3) +#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x) +#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x) + +#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER BIT(4) +#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x) +#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x) + +#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN BIT(5) +#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x) +#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_05 */ +#define SD25G_LANE_LANE_05(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) + +#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0) +#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x) +#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x) + +#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0 GENMASK(5, 4) +#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x) +#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_06 */ +#define SD25G_LANE_LANE_06(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) + +#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0) +#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x) +#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x) + +#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0 GENMASK(7, 4) +#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x) +#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_07 */ +#define SD25G_LANE_LANE_07(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) + +#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0) +#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x) +#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x) + +#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2 BIT(1) +#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x) +#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x) + +#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY BIT(2) +#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x) +#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_09 */ +#define SD25G_LANE_LANE_09(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) + +#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0) +#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x) +#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_0A */ +#define SD25G_LANE_LANE_0A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) + +#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0) +#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x) +#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_0B */ +#define SD25G_LANE_LANE_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) + +#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0) +#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x) +#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x) + +#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST BIT(1) +#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x) +#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x) + +#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0 GENMASK(5, 4) +#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x) +#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_0C */ +#define SD25G_LANE_LANE_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) + +#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) +#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x) +#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x) + +#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN BIT(4) +#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x) +#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x) + +#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD BIT(5) +#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x) +#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_0D */ +#define SD25G_LANE_LANE_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) + +#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0) +#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x) +#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x) + +#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8 BIT(4) +#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x) +#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x) + +#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN BIT(5) +#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x) +#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x) + +#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD BIT(6) +#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x) +#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x) + +#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN BIT(7) +#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x) +#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_0E */ +#define SD25G_LANE_LANE_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) + +#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0) +#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x) +#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x) + +#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD BIT(1) +#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x) +#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x) + +#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG BIT(2) +#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x) +#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x) + +#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0 GENMASK(6, 4) +#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x) +#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_0F */ +#define SD25G_LANE_LANE_0F(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) + +#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0) +#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x) +#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_18 */ +#define SD25G_LANE_LANE_18(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) + +#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0) +#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x) +#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x) + +#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT BIT(1) +#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x) +#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x) + +#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN BIT(2) +#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x) +#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x) + +#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD BIT(3) +#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x) +#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x) + +#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0 GENMASK(6, 4) +#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x) +#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_19 */ +#define SD25G_LANE_LANE_19(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) + +#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0) +#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x) +#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x) + +#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD BIT(1) +#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x) +#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x) + +#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL BIT(2) +#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x) +#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x) + +#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN BIT(3) +#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x) +#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x) + +#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU BIT(4) +#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x) +#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x) + +#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP BIT(5) +#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x) +#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x) + +#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET BIT(6) +#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x) +#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x) + +#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE BIT(7) +#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x) +#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_1A */ +#define SD25G_LANE_LANE_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) + +#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0) +#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x) +#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x) + +#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0 GENMASK(6, 4) +#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x) +#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_1B */ +#define SD25G_LANE_LANE_1B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) + +#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0) +#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x) +#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_1C */ +#define SD25G_LANE_LANE_1C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) + +#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0) +#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x) +#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x) + +#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD BIT(1) +#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x) +#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x) + +#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD BIT(2) +#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x) +#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x) + +#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 GENMASK(7, 4) +#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x) +#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_1D */ +#define SD25G_LANE_LANE_1D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) + +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0) +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x) +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD BIT(1) +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x) +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN BIT(2) +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x) +#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP BIT(3) +#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x) +#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T BIT(4) +#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x) +#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN BIT(5) +#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x) +#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR BIT(6) +#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x) +#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x) + +#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD BIT(7) +#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x) +#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_1E */ +#define SD25G_LANE_LANE_1E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) + +#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0) +#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x) +#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x) + +#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN BIT(4) +#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x) +#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x) + +#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN BIT(5) +#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x) +#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x) + +#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR BIT(6) +#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x) +#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x) + +#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD BIT(7) +#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x) +#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_21 */ +#define SD25G_LANE_LANE_21(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) + +#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0) +#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x) +#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_22 */ +#define SD25G_LANE_LANE_22(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) + +#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0) +#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x) +#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_25 */ +#define SD25G_LANE_LANE_25(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) + +#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0) +#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x) +#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_26 */ +#define SD25G_LANE_LANE_26(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) + +#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0) +#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x) +#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_28 */ +#define SD25G_LANE_LANE_28(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) + +#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0) +#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x) +#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x) + +#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH BIT(1) +#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x) +#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x) + +#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL BIT(2) +#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x) +#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x) + +#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4) +#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x) +#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_2B */ +#define SD25G_LANE_LANE_2B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) + +#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0) +#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x) +#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x) + +#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4) +#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x) +#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x) + +#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU BIT(5) +#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x) +#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_2C */ +#define SD25G_LANE_LANE_2C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) + +#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0) +#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x) +#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x) + +#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER BIT(4) +#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x) +#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_2D */ +#define SD25G_LANE_LANE_2D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) + +#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0) +#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x) +#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x) + +#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4) +#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x) +#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_2E */ +#define SD25G_LANE_LANE_2E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) + +#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0) +#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x) +#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ BIT(1) +#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x) +#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ BIT(2) +#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x) +#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS BIT(3) +#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x) +#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC BIT(4) +#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x) +#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG BIT(5) +#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x) +#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN BIT(6) +#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x) +#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x) + +#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN BIT(7) +#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x) +#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_40 */ +#define SD25G_LANE_LANE_40(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) + +#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0) +#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x) +#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x) + +#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV BIT(1) +#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x) +#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x) + +#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE BIT(2) +#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x) +#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x) + +#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV BIT(3) +#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x) +#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x) + +#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN BIT(4) +#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x) +#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x) + +#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN BIT(5) +#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x) +#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x) + +#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN BIT(6) +#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x) +#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_42 */ +#define SD25G_LANE_LANE_42(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) + +#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0) +#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x) +#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_43 */ +#define SD25G_LANE_LANE_43(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) + +#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0) +#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x) +#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_44 */ +#define SD25G_LANE_LANE_44(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) + +#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0) +#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x) +#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x) + +/* SD25G_TARGET:LANE_GRP_0:LANE_45 */ +#define SD25G_LANE_LANE_45(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) + +#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0) +#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x) +#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x) + +/* SD25G_TARGET:LANE_GRP_1:LANE_DE */ +#define SD25G_LANE_LANE_DE(t) __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) + +#define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0) +#define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x) +#define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x) + +#define SD25G_LANE_LANE_DE_LN_LOL BIT(1) +#define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x) +#define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x) + +#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2) +#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x) +#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x) + +#define SD25G_LANE_LANE_DE_LN_PMA_RXEI BIT(3) +#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\ + FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x) +#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x) + +/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ +#define SD6G_LANE_LANE_DF(t) __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) + +#define SD6G_LANE_LANE_DF_LOL_UDL BIT(0) +#define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ + FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x) +#define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\ + FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x) + +#define SD6G_LANE_LANE_DF_LOL BIT(1) +#define SD6G_LANE_LANE_DF_LOL_SET(x)\ + FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x) +#define SD6G_LANE_LANE_DF_LOL_GET(x)\ + FIELD_GET(SD6G_LANE_LANE_DF_LOL, x) + +#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2) +#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ + FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x) +#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ + FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x) + +#define SD6G_LANE_LANE_DF_SQUELCH BIT(3) +#define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\ + FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x) +#define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ + FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x) + +/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ +#define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4) + +#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0) +#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ + FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x) +#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\ + FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x) + +#define SD_CMU_CMU_00_CFG_PLL_LOL_SET BIT(1) +#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\ + FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x) +#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\ + FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x) + +#define SD_CMU_CMU_00_CFG_PLL_LOS_SET BIT(2) +#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\ + FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x) +#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\ + FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x) + +#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4) +#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\ + FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x) +#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x) + +/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ +#define SD_CMU_CMU_05(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4) + +#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0) +#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x) +#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x) + +#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0 GENMASK(5, 4) +#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\ + FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x) +#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x) + +/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ +#define SD_CMU_CMU_09(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4) + +#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0) +#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ + FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x) +#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\ + FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x) + +#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN BIT(1) +#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x) +#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\ + FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x) + +#define SD_CMU_CMU_09_CFG_SW_8G BIT(4) +#define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\ + FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x) +#define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\ + FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x) + +#define SD_CMU_CMU_09_CFG_SW_10G BIT(5) +#define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\ + FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x) +#define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ + FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x) + +/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ +#define SD_CMU_CMU_0D(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4) + +#define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0) +#define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ + FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x) +#define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\ + FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x) + +#define SD_CMU_CMU_0D_CFG_PD_DIV66 BIT(1) +#define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\ + FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x) +#define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\ + FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x) + +#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD BIT(2) +#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\ + FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x) +#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\ + FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x) + +#define SD_CMU_CMU_0D_CFG_JC_BYP BIT(3) +#define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\ + FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x) +#define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\ + FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x) + +#define SD_CMU_CMU_0D_CFG_REFCK_PD BIT(4) +#define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\ + FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x) +#define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ + FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x) + +/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ +#define SD_CMU_CMU_1B(t) __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4) + +#define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0) +#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ + FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x) +#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x) + +/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ +#define SD_CMU_CMU_1F(t) __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4) + +#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0) +#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x) +#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x) + +#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN BIT(1) +#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x) +#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x) + +#define SD_CMU_CMU_1F_CFG_IC2IP_N BIT(2) +#define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\ + FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x) +#define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\ + FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x) + +#define SD_CMU_CMU_1F_CFG_VTUNE_SEL BIT(3) +#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\ + FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x) +#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ + FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x) + +/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ +#define SD_CMU_CMU_30(t) __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4) + +#define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0) +#define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x) +#define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x) + +/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ +#define SD_CMU_CMU_44(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4) + +#define SD_CMU_CMU_44_R_PLL_RSTN BIT(0) +#define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x) +#define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\ + FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x) + +#define SD_CMU_CMU_44_R_CK_RESETB BIT(1) +#define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\ + FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x) +#define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ + FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x) + +/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ +#define SD_CMU_CMU_45(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4) + +#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0) +#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x) +#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x) + +#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT BIT(1) +#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x) +#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x) + +#define SD_CMU_CMU_45_RESERVED BIT(2) +#define SD_CMU_CMU_45_RESERVED_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_RESERVED, x) +#define SD_CMU_CMU_45_RESERVED_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_RESERVED, x) + +#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT BIT(3) +#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x) +#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x) + +#define SD_CMU_CMU_45_RESERVED_2 BIT(4) +#define SD_CMU_CMU_45_RESERVED_2_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x) +#define SD_CMU_CMU_45_RESERVED_2_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x) + +#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT BIT(5) +#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x) +#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x) + +#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT BIT(6) +#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x) +#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x) + +#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN BIT(7) +#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\ + FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x) +#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x) + +/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ +#define SD_CMU_CMU_47(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4) + +#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) +#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ + FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x) +#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x) + +/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ +#define SD_CMU_CMU_E0(t) __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4) + +#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) +#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ + FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x) +#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x) + +#define SD_CMU_CMU_E0_PLL_LOL_UDL BIT(4) +#define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\ + FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x) +#define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ + FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x) + +/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ +#define SD_CMU_CFG_SD_CMU_CFG(t) __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4) + +#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0) +#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ + FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x) +#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\ + FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x) + +#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST BIT(1) +#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\ + FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x) +#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ + FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x) + +/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ +#define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4) + +#define SD_LANE_SD_SER_RST_SER_RST BIT(0) +#define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x) +#define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x) + +/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ +#define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4) + +#define SD_LANE_SD_DES_RST_DES_RST BIT(0) +#define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x) +#define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x) + +/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ +#define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4) + +#define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0) +#define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x) +#define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x) + +#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST BIT(1) +#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x) +#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x) + +#define SD_LANE_SD_LANE_CFG_TX_REF_SEL GENMASK(5, 4) +#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x) +#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x) + +#define SD_LANE_SD_LANE_CFG_RX_REF_SEL GENMASK(7, 6) +#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x) +#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x) + +#define SD_LANE_SD_LANE_CFG_LANE_RST BIT(8) +#define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x) +#define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x) + +#define SD_LANE_SD_LANE_CFG_LANE_TX_RST BIT(9) +#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x) +#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x) + +#define SD_LANE_SD_LANE_CFG_LANE_RX_RST BIT(10) +#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x) +#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x) + +/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ +#define SD_LANE_SD_LANE_STAT(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4) + +#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0) +#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x) +#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x) + +#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE BIT(1) +#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x) +#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x) + +#define SD_LANE_SD_LANE_STAT_DBG_OBS GENMASK(31, 16) +#define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\ + FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x) +#define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x) + +/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ +#define SD_LANE_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4) + +#define SD_LANE_MISC_SD_125_RST_DIS BIT(0) +#define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ + FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x) +#define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\ + FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x) + +#define SD_LANE_MISC_RX_ENA BIT(1) +#define SD_LANE_MISC_RX_ENA_SET(x)\ + FIELD_PREP(SD_LANE_MISC_RX_ENA, x) +#define SD_LANE_MISC_RX_ENA_GET(x)\ + FIELD_GET(SD_LANE_MISC_RX_ENA, x) + +#define SD_LANE_MISC_MUX_ENA BIT(2) +#define SD_LANE_MISC_MUX_ENA_SET(x)\ + FIELD_PREP(SD_LANE_MISC_MUX_ENA, x) +#define SD_LANE_MISC_MUX_ENA_GET(x)\ + FIELD_GET(SD_LANE_MISC_MUX_ENA, x) + +#define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4) +#define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ + FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x) +#define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ + FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x) + +/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ +#define SD_LANE_M_STAT_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4) + +#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0) +#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ + FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x) +#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\ + FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x) + +#define SD_LANE_M_STAT_MISC_M_LOCK_CNT GENMASK(31, 24) +#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\ + FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x) +#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ + FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x) + +/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ +#define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) + +#define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0) +#define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x) +#define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x) + +/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ +#define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) + +#define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0) +#define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x) +#define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x) + +/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ +#define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) + +#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0) +#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x) +#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x) + +#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST BIT(1) +#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x) +#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x) + +#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4) +#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x) +#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE GENMASK(7, 5) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x) + +#define SD_LANE_25G_SD_LANE_CFG_LANE_RST BIT(8) +#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x) +#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV BIT(9) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN BIT(10) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY BIT(11) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV GENMASK(15, 12) +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN BIT(16) +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY GENMASK(21, 17) +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN BIT(22) +#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING BIT(24) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI BIT(25) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x) + +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x) +#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x) + +/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ +#define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) + +#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0) +#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x) + +#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL GENMASK(5, 3) +#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x) + +#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL GENMASK(8, 6) +#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x) + +#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9) +#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x) +#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x) + +#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV GENMASK(13, 11) +#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x) +#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x) + +#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV GENMASK(16, 14) +#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x) +#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x) + +#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17) +#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x) + +#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20) +#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x) +#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x) + +#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL GENMASK(25, 24) +#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x) + +#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL GENMASK(28, 26) +#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x) + +#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL GENMASK(31, 29) +#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x) +#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x) + +/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ +#define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) + +#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0) +#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x) +#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x) + +#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE BIT(1) +#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x) +#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x) + +#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS GENMASK(31, 16) +#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\ + FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x) +#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x) + +#endif /* _SPARX5_SERDES_REGS_H_ */ diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 71cb10826326..ccb575b13777 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -373,6 +373,36 @@ int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) } EXPORT_SYMBOL_GPL(phy_set_mode_ext); +int phy_set_media(struct phy *phy, enum phy_media media) +{ + int ret; + + if (!phy || !phy->ops->set_media) + return 0; + + mutex_lock(&phy->mutex); + ret = phy->ops->set_media(phy, media); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_set_media); + +int phy_set_speed(struct phy *phy, int speed) +{ + int ret; + + if (!phy || !phy->ops->set_speed) + return 0; + + mutex_lock(&phy->mutex); + ret = phy->ops->set_speed(phy, speed); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_set_speed); + int phy_reset(struct phy *phy) { int ret; diff --git a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c index 9061ece7ff6a..bfff0c8c9130 100644 --- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c @@ -276,8 +276,8 @@ static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy) val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP | HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN | HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP | - HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID | - HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70; + HSUSB_CTRL_UTMI_OTG_VBUS_VALID | HSUSB_CTRL_UTMI_CLK_EN | + HSUSB_CTRL_CLAMP_EN | 0x70; /* use core clock if external reference is not present */ if (!phy_dwc3->xo_clk) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 9cdebe7f26cb..7877f70cf86f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1840,6 +1840,86 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), }; +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +}; + +static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), +}; + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), @@ -2268,6 +2348,8 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), }; +struct qmp_phy; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* phy-type - PCIE/UFS/USB */ @@ -2307,6 +2389,12 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *serdes_tbl_hbr3; int serdes_tbl_hbr3_num; + /* DP PHY callbacks */ + int (*configure_dp_phy)(struct qmp_phy *qphy); + void (*configure_dp_tx)(struct qmp_phy *qphy); + int (*calibrate_dp_phy)(struct qmp_phy *qphy); + void (*dp_aux_init)(struct qmp_phy *qphy); + /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -2423,6 +2511,16 @@ struct qcom_qmp { struct reset_control *ufs_reset; }; +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); + +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -2871,6 +2969,11 @@ static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .has_phy_dp_com_ctrl = true, .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, }; static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { @@ -3123,6 +3226,46 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; +static const struct qmp_phy_cfg sm8250_dpphy_cfg = { + .type = PHY_TYPE_DP, + .nlanes = 1, + + .serdes_tbl = qmp_v4_dp_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), + .tx_tbl = qmp_v4_dp_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +}; + +static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { + .usb_cfg = &sm8250_usb3phy_cfg, + .dp_cfg = &sm8250_dpphy_cfg, +}; + static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -3332,24 +3475,24 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) return 0; } -static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) { writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + qphy->pcs + QSERDES_DP_PHY_PD_CTL); /* Turn on BIAS current for PHY/PLL */ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + qphy->pcs + QSERDES_DP_PHY_PD_CTL); writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | @@ -3357,16 +3500,16 @@ static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); - writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); - writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3); - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4); - writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5); - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6); - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7); - writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8); - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); qphy->dp_aux_cfg = 0; writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | @@ -3375,6 +3518,20 @@ static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); } +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { + { 0x00, 0x0c, 0x15, 0x1a }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { { 0x00, 0x0c, 0x14, 0x19 }, { 0x00, 0x0b, 0x12, 0xff }, @@ -3389,11 +3546,11 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { { 0x1f, 0xff, 0xff, 0xff } }; -static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) +static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, + unsigned int drv_lvl_reg, unsigned int emp_post_reg) { const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; unsigned int v_level = 0, p_level = 0; - u32 bias_en, drvr_en; u8 voltage_swing_cfg, pre_emphasis_cfg; int i; @@ -3402,56 +3559,58 @@ static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) p_level = max(p_level, dp_opts->pre[i]); } - if (dp_opts->lanes == 1) { - bias_en = 0x3e; - drvr_en = 0x13; + if (dp_opts->link_rate <= 2700) { + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; } else { - bias_en = 0x3f; - drvr_en = 0x10; + voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; + pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; } - voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; - pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; - /* TODO: Move check to config check */ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) - return; + return -EINVAL; /* Enable MUX to use Cursor values from these registers */ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; - writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL); - writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); - writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL); - writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); + writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); + writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); + writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); - writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); - writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); - writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); - writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + return 0; } -static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) { - const struct phy_configure_opts_dp *dp_opts = &opts->dp; - struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 bias_en, drvr_en; - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); - if (qphy->dp_opts.set_voltages) { - qcom_qmp_phy_configure_dp_tx(qphy); - qphy->dp_opts.set_voltages = 0; + if (qcom_qmp_phy_configure_dp_swing(qphy, + QSERDES_V3_TX_TX_DRV_LVL, + QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) + return; + + if (dp_opts->lanes == 1) { + bias_en = 0x3e; + drvr_en = 0x13; + } else { + bias_en = 0x3f; + drvr_en = 0x10; } - return 0; + writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); } -static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) +static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) { - const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; - u32 val, phy_vco_div, status; - unsigned long pixel_freq; + u32 val; + bool reverse = false; val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; @@ -3471,9 +3630,22 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); */ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); + + return reverse; +} + +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 phy_vco_div, status; + unsigned long pixel_freq; + + qcom_qmp_phy_configure_dp_mode(qphy); - writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); @@ -3503,11 +3675,11 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); - writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); - writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); @@ -3518,7 +3690,7 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) 10000)) return -ETIMEDOUT; - writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, status, @@ -3527,9 +3699,9 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) 10000)) return -ETIMEDOUT; - writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); udelay(2000); - writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, status, @@ -3542,9 +3714,8 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) * We need to calibrate the aux setting here as many times * as the caller tries */ -static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) { - struct qmp_phy *qphy = phy_get_drvdata(phy); static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; u8 val; @@ -3552,7 +3723,231 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy) qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); val = cfg1_settings[qphy->dp_aux_cfg]; - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + + return 0; +} + +static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) +{ + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qphy->pcs + QSERDES_DP_PHY_PD_CTL); + + /* Turn on BIAS current for PHY/PLL */ + writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); + writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); + qphy->dp_aux_cfg = 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); +} + +static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) +{ + /* Program default values before writing proper values */ + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); + + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); + + qcom_qmp_phy_configure_dp_swing(qphy, + QSERDES_V4_TX_TX_DRV_LVL, + QSERDES_V4_TX_TX_EMP_POST1_LVL); +} + +static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) +{ + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + u32 phy_vco_div, status; + unsigned long pixel_freq; + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + bool reverse; + + writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); + + reverse = qcom_qmp_phy_configure_dp_mode(qphy); + + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div = 0x1; + pixel_freq = 1620000000UL / 2; + break; + case 2700: + phy_vco_div = 0x1; + pixel_freq = 2700000000UL / 2; + break; + case 5400: + phy_vco_div = 0x2; + pixel_freq = 5400000000UL / 4; + break; + case 8100: + phy_vco_div = 0x0; + pixel_freq = 8100000000UL / 6; + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); + + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); + + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); + + writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + /* + * At least for 7nm DP PHY this has to be done after enabling link + * clock. + */ + + if (dp_opts->lanes == 1) { + bias0_en = reverse ? 0x3e : 0x15; + bias1_en = reverse ? 0x15 : 0x3e; + drvr0_en = reverse ? 0x13 : 0x10; + drvr1_en = reverse ? 0x10 : 0x13; + } else if (dp_opts->lanes == 2) { + bias0_en = reverse ? 0x3f : 0x15; + bias1_en = reverse ? 0x15 : 0x3f; + drvr0_en = 0x10; + drvr1_en = 0x10; + } else { + bias0_en = 0x3f; + bias1_en = 0x3f; + drvr0_en = 0x10; + drvr1_en = 0x10; + } + + writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); + writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); + writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); + udelay(2000); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); + + writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); + + writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); + writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); + + return 0; +} + +/* + * We need to calibrate the aux setting here as many times + * as the caller tries + */ +static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) +{ + static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; + u8 val; + + qphy->dp_aux_cfg++; + qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); + val = cfg1_settings[qphy->dp_aux_cfg]; + + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + + return 0; +} + +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + const struct phy_configure_opts_dp *dp_opts = &opts->dp; + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qphy->dp_opts.set_voltages) { + cfg->configure_dp_tx(qphy); + qphy->dp_opts.set_voltages = 0; + } + + return 0; +} + +static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + if (cfg->calibrate_dp_phy) + return cfg->calibrate_dp_phy(qphy); return 0; } @@ -3729,7 +4124,7 @@ static int qcom_qmp_phy_init(struct phy *phy) return ret; if (cfg->type == PHY_TYPE_DP) - qcom_qmp_phy_dp_aux_init(qphy); + cfg->dp_aux_init(qphy); return 0; } @@ -3783,7 +4178,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) /* Configure special DP tx tunings */ if (cfg->type == PHY_TYPE_DP) - qcom_qmp_phy_configure_dp_tx(qphy); + cfg->configure_dp_tx(qphy); qcom_qmp_phy_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); @@ -3802,7 +4197,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) /* Configure link rate, swing, etc. */ if (cfg->type == PHY_TYPE_DP) { - qcom_qmp_phy_configure_dp_phy(qphy); + cfg->configure_dp_phy(qphy); } else { qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); if (cfg->pcs_tbl_sec) @@ -3874,7 +4269,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) if (cfg->type == PHY_TYPE_DP) { /* Assert DP PHY power down */ - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); } else { /* PHY reset */ if (!cfg->no_pcs_sw_reset) @@ -4578,6 +4973,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { .compatible = "qcom,sm8250-qmp-usb3-phy", .data = &sm8250_usb3phy_cfg, }, { + .compatible = "qcom,sm8250-qmp-usb3-dp-phy", + /* It's a combo phy */ + }, { .compatible = "qcom,sm8250-qmp-usb3-uni-phy", .data = &sm8250_usb3_uniphy_cfg, }, { @@ -4611,6 +5009,10 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { .compatible = "qcom,sc7180-qmp-usb3-dp-phy", .data = &sc7180_usb3dpphy_cfg, }, + { + .compatible = "qcom,sm8250-qmp-usb3-dp-phy", + .data = &sm8250_usb3dpphy_cfg, + }, { } }; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 71ce3aa174ae..67bd2dd0d8c5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -349,13 +349,13 @@ #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 -/* Only for QMP V3 PHY - DP PHY registers */ -#define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 -#define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 -#define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 -#define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c -#define QSERDES_V3_DP_PHY_CFG 0x010 -#define QSERDES_V3_DP_PHY_PD_CTL 0x018 +/* QMP PHY - DP PHY registers */ +#define QSERDES_DP_PHY_REVISION_ID0 0x000 +#define QSERDES_DP_PHY_REVISION_ID1 0x004 +#define QSERDES_DP_PHY_REVISION_ID2 0x008 +#define QSERDES_DP_PHY_REVISION_ID3 0x00c +#define QSERDES_DP_PHY_CFG 0x010 +#define QSERDES_DP_PHY_PD_CTL 0x018 # define DP_PHY_PD_CTL_PWRDN 0x001 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 @@ -363,18 +363,19 @@ # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 -#define QSERDES_V3_DP_PHY_MODE 0x01c -#define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 -#define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 -#define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 -#define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c -#define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 -#define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 -#define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 -#define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c -#define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 -#define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 +#define QSERDES_DP_PHY_MODE 0x01c +#define QSERDES_DP_PHY_AUX_CFG0 0x020 +#define QSERDES_DP_PHY_AUX_CFG1 0x024 +#define QSERDES_DP_PHY_AUX_CFG2 0x028 +#define QSERDES_DP_PHY_AUX_CFG3 0x02c +#define QSERDES_DP_PHY_AUX_CFG4 0x030 +#define QSERDES_DP_PHY_AUX_CFG5 0x034 +#define QSERDES_DP_PHY_AUX_CFG6 0x038 +#define QSERDES_DP_PHY_AUX_CFG7 0x03c +#define QSERDES_DP_PHY_AUX_CFG8 0x040 +#define QSERDES_DP_PHY_AUX_CFG9 0x044 +/* Only for QMP V3 PHY - DP PHY registers */ #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 # define PHY_AUX_STOP_ERR_MASK 0x01 # define PHY_AUX_DEC_ERR_MASK 0x02 @@ -396,6 +397,7 @@ #define QSERDES_V3_DP_PHY_STATUS 0x0c0 /* Only for QMP V4 PHY - QSERDES COM registers */ +#define QSERDES_V4_COM_BG_TIMER 0x00c #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 #define QSERDES_V4_COM_SSC_PER1 0x01c #define QSERDES_V4_COM_SSC_PER2 0x020 @@ -403,7 +405,9 @@ #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 #define QSERDES_V4_COM_CLK_ENABLE1 0x048 +#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 #define QSERDES_V4_COM_PLL_IVCO 0x058 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 @@ -414,6 +418,7 @@ #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 @@ -427,16 +432,24 @@ #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V4_COM_CMN_STATUS 0x140 #define QSERDES_V4_COM_CLK_SELECT 0x154 #define QSERDES_V4_COM_HSCLK_SEL 0x158 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V4_COM_CORE_CLK_EN 0x174 +#define QSERDES_V4_COM_C_READY_STATUS 0x178 +#define QSERDES_V4_COM_CMN_CONFIG 0x17c #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 @@ -445,19 +458,32 @@ #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 /* Only for QMP V4 PHY - TX registers */ +#define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c +#define QSERDES_V4_TX_TX_DRV_LVL 0x14 +#define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c +#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 +#define QSERDES_V4_TX_TX_BAND 0x24 +#define QSERDES_V4_TX_INTERFACE_SELECT 0x2c #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 +#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 +#define QSERDES_V4_TX_TX_POL_INV 0x5c +#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 #define QSERDES_V4_TX_LANE_MODE_1 0x84 #define QSERDES_V4_TX_LANE_MODE_2 0x88 #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c +#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 +#define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 -#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 -#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 +#define QSERDES_V4_TX_VMODE_CTRL1 0xe8 +#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 /* Only for QMP V4 PHY - RX registers */ #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 @@ -514,6 +540,17 @@ #define QSERDES_V4_RX_DCC_CTRL1 0x1bc #define QSERDES_V4_RX_VTH_CODE 0x1c4 +/* Only for QMP V4 PHY - DP PHY registers */ +#define QSERDES_V4_DP_PHY_CFG_1 0x014 +#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 +#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 +#define QSERDES_V4_DP_PHY_VCO_DIV 0x070 +#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 +#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c +#define QSERDES_V4_DP_PHY_SPARE0 0x0c8 +#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 +#define QSERDES_V4_DP_PHY_STATUS 0x0dc + /* Only for QMP V4 PHY - UFS PCS registers */ #define QPHY_V4_PCS_UFS_PHY_START 0x000 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs.c b/drivers/phy/qualcomm/phy-qcom-usb-hs.c index 327df1a99f77..5c6c17673396 100644 --- a/drivers/phy/qualcomm/phy-qcom-usb-hs.c +++ b/drivers/phy/qualcomm/phy-qcom-usb-hs.c @@ -56,6 +56,7 @@ static int qcom_usb_hs_phy_set_mode(struct phy *phy, fallthrough; case PHY_MODE_USB_DEVICE: val |= ULPI_INT_SESS_VALID; + break; default: break; } diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index 9a610b414b1f..753cb5bab930 100644 --- a/drivers/phy/ralink/phy-mt7621-pci.c +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -62,7 +62,7 @@ #define RG_PE1_FRC_MSTCKDIV BIT(5) -#define XTAL_MASK GENMASK(7, 6) +#define XTAL_MASK GENMASK(8, 6) #define MAX_PHYS 2 @@ -319,9 +319,9 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev) return PTR_ERR(phy->regmap); phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops); - if (IS_ERR(phy)) { + if (IS_ERR(phy->phy)) { dev_err(dev, "failed to create phy\n"); - return PTR_ERR(phy); + return PTR_ERR(phy->phy); } phy_set_drvdata(phy->phy, phy); diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 70a31251b202..d2bbdc96a167 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -1180,6 +1180,7 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) dev_err(dev, "failed to create phy: %pOFn\n", child_np); pm_runtime_disable(dev); + of_node_put(child_np); return PTR_ERR(phy); } diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index b32f44ff9033..3fc3d0781fb8 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -36,6 +36,7 @@ config PHY_STIH407_USB config PHY_STM32_USBPHYC tristate "STMicroelectronics STM32 USB HS PHY Controller driver" depends on ARCH_STM32 || COMPILE_TEST + depends on COMMON_CLK select GENERIC_PHY help Enable this to support the High-Speed USB transceivers that are part diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c index d08fbb180e43..c184f4e34584 100644 --- a/drivers/phy/st/phy-stm32-usbphyc.c +++ b/drivers/phy/st/phy-stm32-usbphyc.c @@ -7,6 +7,7 @@ */ #include <linux/bitfield.h> #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/kernel.h> @@ -70,6 +71,7 @@ struct stm32_usbphyc { struct regulator *vdda1v1; struct regulator *vdda1v8; atomic_t n_pll_cons; + struct clk_hw clk48_hw; int switch_setup; }; @@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = { .owner = THIS_MODULE, }; +static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw) +{ + struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw); + + return stm32_usbphyc_pll_enable(usbphyc); +} + +static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw) +{ + struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw); + + stm32_usbphyc_pll_disable(usbphyc); +} + +static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + return 48000000; +} + +static const struct clk_ops usbphyc_clk48_ops = { + .prepare = stm32_usbphyc_clk48_prepare, + .unprepare = stm32_usbphyc_clk48_unprepare, + .recalc_rate = stm32_usbphyc_clk48_recalc_rate, +}; + +static void stm32_usbphyc_clk48_unregister(void *data) +{ + struct stm32_usbphyc *usbphyc = data; + + of_clk_del_provider(usbphyc->dev->of_node); + clk_hw_unregister(&usbphyc->clk48_hw); +} + +static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc) +{ + struct device_node *node = usbphyc->dev->of_node; + struct clk_init_data init = { }; + int ret = 0; + + init.name = "ck_usbo_48m"; + init.ops = &usbphyc_clk48_ops; + + usbphyc->clk48_hw.init = &init; + + ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw); + if (ret) + clk_hw_unregister(&usbphyc->clk48_hw); + + return ret; +} + static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc, u32 utmi_switch) { @@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device *pdev) goto clk_disable; } + ret = stm32_usbphyc_clk48_register(usbphyc); + if (ret) { + dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret); + goto clk_disable; + } + version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION); dev_info(dev, "registered rev:%lu.%lu\n", FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version)); @@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device *pdev) if (usbphyc->phys[port]->active) stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy); + stm32_usbphyc_clk48_unregister(usbphyc); + clk_disable_unprepare(usbphyc->clk); return 0; diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c9cfafe89cbf..2b354680a272 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -7,6 +7,7 @@ */ #include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-ti.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/gpio.h> @@ -26,6 +27,11 @@ #define WIZ_SERDES_RST 0x40c #define WIZ_SERDES_TYPEC 0x410 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) +#define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) + +#define WIZ_MAX_INPUT_CLOCKS 4 +/* To include mux clocks, divider clocks and gate clocks */ +#define WIZ_MAX_OUTPUT_CLOCKS 32 #define WIZ_MAX_LANES 4 #define WIZ_MUX_NUM_CLOCKS 3 @@ -52,8 +58,16 @@ enum wiz_refclk_div_sel { CMN_REFCLK1_DIG_DIV, }; +enum wiz_clock_input { + WIZ_CORE_REFCLK, + WIZ_EXT_REFCLK, + WIZ_CORE_REFCLK1, + WIZ_EXT_REFCLK1, +}; + static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); +static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); static const struct reg_field pll1_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 29, 29); static const struct reg_field pll0_refclk_mux_sel = @@ -70,6 +84,12 @@ static const struct reg_field pma_cmn_refclk_dig_div = REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); static const struct reg_field pma_cmn_refclk1_dig_div = REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); +static const char * const output_clk_names[] = { + [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", + [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", + [TI_WIZ_REFCLK_DIG] = "refclk-dig", + [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", +}; static const struct reg_field p_enable[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(0), 30, 31), @@ -101,13 +121,34 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 24, 25), }; +static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 22, 23), + REG_FIELD(WIZ_LANECTL(1), 22, 23), + REG_FIELD(WIZ_LANECTL(2), 22, 23), + REG_FIELD(WIZ_LANECTL(3), 22, 23), +}; + +static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANEDIV(0), 16, 22), + REG_FIELD(WIZ_LANEDIV(1), 16, 22), + REG_FIELD(WIZ_LANEDIV(2), 16, 22), + REG_FIELD(WIZ_LANEDIV(3), 16, 22), +}; + +static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANEDIV(0), 0, 8), + REG_FIELD(WIZ_LANEDIV(1), 0, 8), + REG_FIELD(WIZ_LANEDIV(2), 0, 8), + REG_FIELD(WIZ_LANEDIV(3), 0, 8), +}; + static const struct reg_field typec_ln10_swap = REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); struct wiz_clk_mux { struct clk_hw hw; struct regmap_field *field; - u32 *table; + const u32 *table; struct clk_init_data clk_data; }; @@ -123,18 +164,26 @@ struct wiz_clk_divider { #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) struct wiz_clk_mux_sel { - struct regmap_field *field; - u32 table[4]; + u32 table[WIZ_MAX_INPUT_CLOCKS]; const char *node_name; + u32 num_parents; + u32 parents[WIZ_MAX_INPUT_CLOCKS]; }; struct wiz_clk_div_sel { - struct regmap_field *field; - const struct clk_div_table *table; + const struct clk_div_table *table; const char *node_name; }; -static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { +struct wiz_phy_en_refclk { + struct clk_hw hw; + struct regmap_field *phy_en_refclk; + struct clk_init_data clk_data; +}; + +#define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) + +static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { { /* * Mux value to be configured for each of the input clocks @@ -153,20 +202,26 @@ static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { }, }; -static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { +static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { { /* * Mux value to be configured for each of the input clocks * in the order populated in device tree */ + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, .table = { 1, 0 }, .node_name = "pll0-refclk", }, { + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, .table = { 1, 0 }, .node_name = "pll1-refclk", }, { + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, .table = { 1, 0 }, .node_name = "refclk-dig", }, @@ -179,7 +234,7 @@ static const struct clk_div_table clk_div_table[] = { { .val = 3, .div = 8, }, }; -static struct wiz_clk_div_sel clk_div_sel[] = { +static const struct wiz_clk_div_sel clk_div_sel[] = { { .table = clk_div_table, .node_name = "cmn-refclk-dig-div", @@ -193,6 +248,7 @@ static struct wiz_clk_div_sel clk_div_sel[] = { enum wiz_type { J721E_WIZ_16G, J721E_WIZ_10G, + AM64_WIZ_10G, }; #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ @@ -201,19 +257,25 @@ enum wiz_type { struct wiz { struct regmap *regmap; enum wiz_type type; - struct wiz_clk_mux_sel *clk_mux_sel; - struct wiz_clk_div_sel *clk_div_sel; + const struct wiz_clk_mux_sel *clk_mux_sel; + const struct wiz_clk_div_sel *clk_div_sel; unsigned int clk_div_sel_num; struct regmap_field *por_en; struct regmap_field *phy_reset_n; + struct regmap_field *phy_en_refclk; struct regmap_field *p_enable[WIZ_MAX_LANES]; struct regmap_field *p_align[WIZ_MAX_LANES]; struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; + struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; + struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; + struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; struct regmap_field *pma_cmn_refclk1_dig_div; + struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; + struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; struct regmap_field *typec_ln10_swap; struct device *dev; @@ -223,6 +285,9 @@ struct wiz { struct gpio_desc *gpio_typec_dir; int typec_dir_delay; u32 lane_phy_type[WIZ_MAX_LANES]; + struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; + struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; + struct clk_onecell_data clk_data; }; static int wiz_reset(struct wiz *wiz) @@ -242,6 +307,27 @@ static int wiz_reset(struct wiz *wiz) return 0; } +static int wiz_p_mac_div_sel(struct wiz *wiz) +{ + u32 num_lanes = wiz->num_lanes; + int ret; + int i; + + for (i = 0; i < num_lanes; i++) { + if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { + ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); + if (ret) + return ret; + + ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); + if (ret) + return ret; + } + } + + return 0; +} + static int wiz_mode_select(struct wiz *wiz) { u32 num_lanes = wiz->num_lanes; @@ -252,8 +338,10 @@ static int wiz_mode_select(struct wiz *wiz) for (i = 0; i < num_lanes; i++) { if (wiz->lane_phy_type[i] == PHY_TYPE_DP) mode = LANE_MODE_GEN1; + else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) + mode = LANE_MODE_GEN2; else - mode = LANE_MODE_GEN4; + continue; ret = regmap_field_write(wiz->p_standard_mode[i], mode); if (ret) @@ -299,6 +387,12 @@ static int wiz_init(struct wiz *wiz) return ret; } + ret = wiz_p_mac_div_sel(wiz); + if (ret) { + dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); + return ret; + } + ret = wiz_init_raw_interface(wiz, true); if (ret) { dev_err(dev, "WIZ interface initialization failed\n"); @@ -310,8 +404,6 @@ static int wiz_init(struct wiz *wiz) static int wiz_regfield_init(struct wiz *wiz) { - struct wiz_clk_mux_sel *clk_mux_sel; - struct wiz_clk_div_sel *clk_div_sel; struct regmap *regmap = wiz->regmap; int num_lanes = wiz->num_lanes; struct device *dev = wiz->dev; @@ -344,54 +436,49 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->pma_cmn_refclk_mode); } - clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; - clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, - pma_cmn_refclk_dig_div); - if (IS_ERR(clk_div_sel->field)) { + wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); + if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); - return PTR_ERR(clk_div_sel->field); + return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); } if (wiz->type == J721E_WIZ_16G) { - clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; - clk_div_sel->field = + wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk1_dig_div); - if (IS_ERR(clk_div_sel->field)) { + if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); - return PTR_ERR(clk_div_sel->field); + return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); } } - clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; - clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, - pll0_refclk_mux_sel); - if (IS_ERR(clk_mux_sel->field)) { + wiz->mux_sel_field[PLL0_REFCLK] = + devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel); + if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); - return PTR_ERR(clk_mux_sel->field); + return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); } - clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; - clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, - pll1_refclk_mux_sel); - if (IS_ERR(clk_mux_sel->field)) { + wiz->mux_sel_field[PLL1_REFCLK] = + devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel); + if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); - return PTR_ERR(clk_mux_sel->field); + return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); } - clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; - if (wiz->type == J721E_WIZ_10G) - clk_mux_sel->field = + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) + wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap, refclk_dig_sel_10g); else - clk_mux_sel->field = + wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap, refclk_dig_sel_16g); - if (IS_ERR(clk_mux_sel->field)) { + if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); - return PTR_ERR(clk_mux_sel->field); + return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); } for (i = 0; i < num_lanes; i++) { @@ -424,6 +511,28 @@ static int wiz_regfield_init(struct wiz *wiz) i); return PTR_ERR(wiz->p_standard_mode[i]); } + + wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); + if (IS_ERR(wiz->p0_fullrt_div[i])) { + dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); + return PTR_ERR(wiz->p0_fullrt_div[i]); + } + + wiz->p_mac_div_sel0[i] = + devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); + if (IS_ERR(wiz->p_mac_div_sel0[i])) { + dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", + i); + return PTR_ERR(wiz->p_mac_div_sel0[i]); + } + + wiz->p_mac_div_sel1[i] = + devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); + if (IS_ERR(wiz->p_mac_div_sel1[i])) { + dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", + i); + return PTR_ERR(wiz->p_mac_div_sel1[i]); + } } wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, @@ -433,6 +542,76 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->typec_ln10_swap); } + wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); + if (IS_ERR(wiz->phy_en_refclk)) { + dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); + return PTR_ERR(wiz->phy_en_refclk); + } + + return 0; +} + +static int wiz_phy_en_refclk_enable(struct clk_hw *hw) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); + struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; + + regmap_field_write(phy_en_refclk, 1); + + return 0; +} + +static void wiz_phy_en_refclk_disable(struct clk_hw *hw) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); + struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; + + regmap_field_write(phy_en_refclk, 0); +} + +static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); + struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; + int val; + + regmap_field_read(phy_en_refclk, &val); + + return !!val; +} + +static const struct clk_ops wiz_phy_en_refclk_ops = { + .enable = wiz_phy_en_refclk_enable, + .disable = wiz_phy_en_refclk_disable, + .is_enabled = wiz_phy_en_refclk_is_enabled, +}; + +static int wiz_phy_en_refclk_register(struct wiz *wiz) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk; + struct device *dev = wiz->dev; + struct clk_init_data *init; + struct clk *clk; + + wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); + if (!wiz_phy_en_refclk) + return -ENOMEM; + + init = &wiz_phy_en_refclk->clk_data; + + init->ops = &wiz_phy_en_refclk_ops; + init->flags = 0; + init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK]; + + wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; + wiz_phy_en_refclk->hw.init = init; + + clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; + return 0; } @@ -443,7 +622,7 @@ static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) unsigned int val; regmap_field_read(field, &val); - return clk_mux_val_to_index(hw, mux->table, 0, val); + return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); } static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) @@ -461,8 +640,69 @@ static const struct clk_ops wiz_clk_mux_ops = { .get_parent = wiz_clk_mux_get_parent, }; -static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, - struct regmap_field *field, u32 *table) +static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, + const struct wiz_clk_mux_sel *mux_sel, int clk_index) +{ + struct device *dev = wiz->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + struct wiz_clk_mux *mux; + char clk_name[100]; + struct clk *clk; + int ret = 0, i; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = mux_sel->num_parents; + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + for (i = 0; i < num_parents; i++) { + clk = wiz->input_clks[mux_sel->parents[i]]; + if (IS_ERR_OR_NULL(clk)) { + dev_err(dev, "Failed to get parent clk for %s\n", + output_clk_names[clk_index]); + ret = -EINVAL; + goto err; + } + parent_names[i] = __clk_get_name(clk); + } + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); + + init = &mux->clk_data; + + init->ops = &wiz_clk_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->field = field; + mux->table = mux_sel->table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto err; + } + + wiz->output_clks[clk_index] = clk; + +err: + kfree(parent_names); + + return ret; +} + +static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, + struct regmap_field *field, const u32 *table) { struct device *dev = wiz->dev; struct clk_init_data *init; @@ -606,20 +846,70 @@ static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) { - struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct device *dev = wiz->dev; struct device_node *clk_node; int i; + if (wiz->type == AM64_WIZ_10G) { + of_clk_del_provider(dev->of_node); + return; + } + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); of_clk_del_provider(clk_node); of_node_put(clk_node); } + + for (i = 0; i < wiz->clk_div_sel_num; i++) { + clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); + of_clk_del_provider(clk_node); + of_node_put(clk_node); + } + + of_clk_del_provider(wiz->dev->of_node); +} + +static int wiz_clock_register(struct wiz *wiz) +{ + const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct device *dev = wiz->dev; + struct device_node *node = dev->of_node; + int clk_index; + int ret; + int i; + + if (wiz->type != AM64_WIZ_10G) + return 0; + + clk_index = TI_WIZ_PLL0_REFCLK; + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { + ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); + if (ret) { + dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); + return ret; + } + } + + ret = wiz_phy_en_refclk_register(wiz); + if (ret) { + dev_err(dev, "Failed to add phy-en-refclk\n"); + return ret; + } + + wiz->clk_data.clks = wiz->output_clks; + wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); + if (ret) + dev_err(dev, "Failed to add clock provider: %s\n", node->name); + + return ret; } static int wiz_clock_init(struct wiz *wiz, struct device_node *node) { - struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; struct device *dev = wiz->dev; struct device_node *clk_node; const char *node_name; @@ -634,6 +924,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) ret = PTR_ERR(clk); return ret; } + wiz->input_clks[WIZ_CORE_REFCLK] = clk; rate = clk_get_rate(clk); if (rate >= 100000000) @@ -647,6 +938,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) ret = PTR_ERR(clk); return ret; } + wiz->input_clks[WIZ_EXT_REFCLK] = clk; rate = clk_get_rate(clk); if (rate >= 100000000) @@ -654,6 +946,13 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) else regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); + if (wiz->type == AM64_WIZ_10G) { + ret = wiz_clock_register(wiz); + if (ret) + dev_err(dev, "Failed to register wiz clocks\n"); + return ret; + } + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { node_name = clk_mux_sel[i].node_name; clk_node = of_get_child_by_name(node, node_name); @@ -663,8 +962,8 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) goto err; } - ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, - clk_mux_sel[i].table); + ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], + clk_mux_sel[i].table); if (ret) { dev_err(dev, "Failed to register %s clock\n", node_name); @@ -684,7 +983,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) goto err; } - ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, + ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], clk_div_sel[i].table); if (ret) { dev_err(dev, "Failed to register %s clock\n", @@ -719,6 +1018,17 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, return ret; } +static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) +{ + if (wiz->type != AM64_WIZ_10G) + return 0; + + if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + + return 0; +} + static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { @@ -742,6 +1052,10 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, return ret; } + ret = wiz_phy_fullrt_div(wiz, id - 1); + if (ret) + return ret; + if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); else @@ -769,6 +1083,9 @@ static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G }, + { + .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G + }, {} }; MODULE_DEVICE_TABLE(of, wiz_id_table); @@ -787,11 +1104,17 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) u32 reg, num_lanes = 1, phy_type = PHY_NONE; int ret, i; + if (!(of_node_name_eq(subnode, "phy") || + of_node_name_eq(subnode, "link"))) + continue; + ret = of_property_read_u32(subnode, "reg", ®); if (ret) { + of_node_put(subnode); dev_err(dev, "%s: Reading \"reg\" from \"%s\" failed: %d\n", __func__, subnode->name, ret); + of_node_put(subnode); return ret; } of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); @@ -813,13 +1136,14 @@ static int wiz_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct platform_device *serdes_pdev; + bool already_configured = false; struct device_node *child_node; struct regmap *regmap; struct resource res; void __iomem *base; struct wiz *wiz; + int ret, val, i; u32 num_lanes; - int ret; wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); if (!wiz) @@ -900,14 +1224,14 @@ static int wiz_probe(struct platform_device *pdev) wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes; - if (wiz->type == J721E_WIZ_10G) + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) wiz->clk_mux_sel = clk_mux_sel_10g; else wiz->clk_mux_sel = clk_mux_sel_16g; wiz->clk_div_sel = clk_div_sel; - if (wiz->type == J721E_WIZ_10G) + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; else wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; @@ -947,27 +1271,34 @@ static int wiz_probe(struct platform_device *pdev) goto err_get_sync; } + for (i = 0; i < wiz->num_lanes; i++) { + regmap_field_read(wiz->p_enable[i], &val); + if (val & (P_ENABLE | P_ENABLE_FORCE)) { + already_configured = true; + break; + } + } + + if (!already_configured) { + ret = wiz_init(wiz); + if (ret) { + dev_err(dev, "WIZ initialization failed\n"); + goto err_wiz_init; + } + } + serdes_pdev = of_platform_device_create(child_node, NULL, dev); if (!serdes_pdev) { dev_WARN(dev, "Unable to create SERDES platform device\n"); ret = -ENOMEM; - goto err_pdev_create; - } - wiz->serdes_pdev = serdes_pdev; - - ret = wiz_init(wiz); - if (ret) { - dev_err(dev, "WIZ initialization failed\n"); goto err_wiz_init; } + wiz->serdes_pdev = serdes_pdev; of_node_put(child_node); return 0; err_wiz_init: - of_platform_device_destroy(&serdes_pdev->dev, NULL); - -err_pdev_create: wiz_clock_cleanup(wiz, node); err_get_sync: diff --git a/drivers/phy/ti/phy-tusb1210.c b/drivers/phy/ti/phy-tusb1210.c index d8d0cc11d187..a63213f5972a 100644 --- a/drivers/phy/ti/phy-tusb1210.c +++ b/drivers/phy/ti/phy-tusb1210.c @@ -7,15 +7,16 @@ * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com> */ #include <linux/module.h> +#include <linux/bitfield.h> #include <linux/ulpi/driver.h> #include <linux/ulpi/regs.h> #include <linux/gpio/consumer.h> #include <linux/phy/ulpi_phy.h> #define TUSB1210_VENDOR_SPECIFIC2 0x80 -#define TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT 0 -#define TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT 4 -#define TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT 6 +#define TUSB1210_VENDOR_SPECIFIC2_IHSTX_MASK GENMASK(3, 0) +#define TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_MASK GENMASK(5, 4) +#define TUSB1210_VENDOR_SPECIFIC2_DP_MASK BIT(6) struct tusb1210 { struct ulpi *ulpi; @@ -118,22 +119,22 @@ static int tusb1210_probe(struct ulpi *ulpi) * diagram optimization and DP/DM swap. */ + reg = ulpi_read(ulpi, TUSB1210_VENDOR_SPECIFIC2); + /* High speed output drive strength configuration */ - device_property_read_u8(&ulpi->dev, "ihstx", &val); - reg = val << TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT; + if (!device_property_read_u8(&ulpi->dev, "ihstx", &val)) + u8p_replace_bits(®, val, (u8)TUSB1210_VENDOR_SPECIFIC2_IHSTX_MASK); /* High speed output impedance configuration */ - device_property_read_u8(&ulpi->dev, "zhsdrv", &val); - reg |= val << TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT; + if (!device_property_read_u8(&ulpi->dev, "zhsdrv", &val)) + u8p_replace_bits(®, val, (u8)TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_MASK); /* DP/DM swap control */ - device_property_read_u8(&ulpi->dev, "datapolarity", &val); - reg |= val << TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT; + if (!device_property_read_u8(&ulpi->dev, "datapolarity", &val)) + u8p_replace_bits(®, val, (u8)TUSB1210_VENDOR_SPECIFIC2_DP_MASK); - if (reg) { - ulpi_write(ulpi, TUSB1210_VENDOR_SPECIFIC2, reg); - tusb->vendor_specific2 = reg; - } + ulpi_write(ulpi, TUSB1210_VENDOR_SPECIFIC2, reg); + tusb->vendor_specific2 = reg; tusb->phy = ulpi_phy_create(ulpi, &phy_ops); if (IS_ERR(tusb->phy)) diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqmp.c index 2b65f84a5f89..35652152ce5d 100644 --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -208,6 +208,7 @@ struct xpsgtr_phy { * @gtr_mutex: mutex for locking * @phys: PHY lanes * @refclk_sscs: spread spectrum settings for the reference clocks + * @clk: reference clocks * @tx_term_fix: fix for GT issue * @saved_icm_cfg0: stored value of ICM CFG0 register * @saved_icm_cfg1: stored value of ICM CFG1 register @@ -219,6 +220,7 @@ struct xpsgtr_dev { struct mutex gtr_mutex; /* mutex for locking */ struct xpsgtr_phy phys[NUM_LANES]; const struct xpsgtr_ssc *refclk_sscs[NUM_LANES]; + struct clk *clk[NUM_LANES]; bool tx_term_fix; unsigned int saved_icm_cfg0; unsigned int saved_icm_cfg1; @@ -818,11 +820,15 @@ static struct phy *xpsgtr_xlate(struct device *dev, static int __maybe_unused xpsgtr_suspend(struct device *dev) { struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); + unsigned int i; /* Save the snapshot ICM_CFG registers. */ gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); + for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) + clk_disable_unprepare(gtr_dev->clk[i]); + return 0; } @@ -832,6 +838,13 @@ static int __maybe_unused xpsgtr_resume(struct device *dev) unsigned int icm_cfg0, icm_cfg1; unsigned int i; bool skip_phy_init; + int err; + + for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) { + err = clk_prepare_enable(gtr_dev->clk[i]); + if (err) + goto err_clk_put; + } icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); @@ -852,6 +865,12 @@ static int __maybe_unused xpsgtr_resume(struct device *dev) gtr_dev->phys[i].skip_phy_init = skip_phy_init; return 0; + +err_clk_put: + while (i--) + clk_disable_unprepare(gtr_dev->clk[i]); + + return err; } static const struct dev_pm_ops xpsgtr_pm_ops = { @@ -865,6 +884,7 @@ static const struct dev_pm_ops xpsgtr_pm_ops = { static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev) { unsigned int refclk; + int ret; for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { unsigned long rate; @@ -874,14 +894,22 @@ static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev) snprintf(name, sizeof(name), "ref%u", refclk); clk = devm_clk_get_optional(gtr_dev->dev, name); - if (IS_ERR(clk)) - return dev_err_probe(gtr_dev->dev, PTR_ERR(clk), - "Failed to get reference clock %u\n", - refclk); + if (IS_ERR(clk)) { + ret = dev_err_probe(gtr_dev->dev, PTR_ERR(clk), + "Failed to get reference clock %u\n", + refclk); + goto err_clk_put; + } if (!clk) continue; + ret = clk_prepare_enable(clk); + if (ret) + goto err_clk_put; + + gtr_dev->clk[refclk] = clk; + /* * Get the spread spectrum (SSC) settings for the reference * clock rate. @@ -899,11 +927,18 @@ static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev) dev_err(gtr_dev->dev, "Invalid rate %lu for reference clock %u\n", rate, refclk); - return -EINVAL; + ret = -EINVAL; + goto err_clk_put; } } return 0; + +err_clk_put: + while (refclk--) + clk_disable_unprepare(gtr_dev->clk[refclk]); + + return ret; } static int xpsgtr_probe(struct platform_device *pdev) @@ -912,6 +947,7 @@ static int xpsgtr_probe(struct platform_device *pdev) struct xpsgtr_dev *gtr_dev; struct phy_provider *provider; unsigned int port; + unsigned int i; int ret; gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); @@ -951,7 +987,8 @@ static int xpsgtr_probe(struct platform_device *pdev) phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); if (IS_ERR(phy)) { dev_err(&pdev->dev, "failed to create PHY\n"); - return PTR_ERR(phy); + ret = PTR_ERR(phy); + goto err_clk_put; } gtr_phy->phy = phy; @@ -962,9 +999,16 @@ static int xpsgtr_probe(struct platform_device *pdev) provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); if (IS_ERR(provider)) { dev_err(&pdev->dev, "registering provider failed\n"); - return PTR_ERR(provider); + ret = PTR_ERR(provider); + goto err_clk_put; } return 0; + +err_clk_put: + for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) + clk_disable_unprepare(gtr_dev->clk[i]); + + return ret; } static const struct of_device_id xpsgtr_of_match[] = { |