diff options
| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2018-09-21 21:26:29 +0900 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-09-28 15:11:08 +0200 |
| commit | eb757fff08b8c57c22643c65add0dc1a570d1342 (patch) | |
| tree | adfc3e9aa97289c793b764c0574a2515bb3280fd /drivers/usb/renesas_usbhs | |
| parent | 91b20c5a5be0088f9534483276f86230c3a5872f (diff) | |
Revert "usb: renesas_usbhs: set the mode by using extcon state for non-otg channel"
This reverts commit cd14247d5c14b9b20bb3d3dfcaa899ca22c8dccc.
R-Car D3 can use OTG mode in fact. So, the commit doesn't need anymore.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/renesas_usbhs')
| -rw-r--r-- | drivers/usb/renesas_usbhs/rcar3.c | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c index b9a8453a5e68..50e5fb55c8a0 100644 --- a/drivers/usb/renesas_usbhs/rcar3.c +++ b/drivers/usb/renesas_usbhs/rcar3.c @@ -27,7 +27,6 @@ * Remarks: bit[31:11] and bit[9:6] should be 0 */ #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */ -#define UGCTRL2_USB0SEL_EHCI 0x00000010 #define UGCTRL2_USB0SEL_HSUSB 0x00000020 #define UGCTRL2_USB0SEL_OTG 0x00000030 #define UGCTRL2_VBUSSEL 0x00000400 @@ -50,14 +49,6 @@ static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val) usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3); } -static void usbhs_rcar3_set_usbsel(struct usbhs_priv *priv, bool ehci) -{ - if (ehci) - usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_EHCI); - else - usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB); -} - static int usbhs_rcar3_power_ctrl(struct platform_device *pdev, void __iomem *base, int enable) { @@ -83,14 +74,10 @@ static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev, struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev); u32 val; int timeout = 1000; - bool is_host = false; if (enable) { usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */ - if (priv->edev) - is_host = extcon_get_state(priv->edev, EXTCON_USB_HOST); - - usbhs_rcar3_set_usbsel(priv, is_host); + usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB); usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM); do { |