diff options
| author | Weike Chen <alvin.chen@intel.com> | 2014-11-26 02:35:10 -0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-11-26 18:07:45 +0000 |
| commit | e5262d0568dc9e10de79a726dfd7edb712a2c10b (patch) | |
| tree | fb8cd4ca58e8f0ef1b1a016ac88139401ed55cfe /drivers/spi/spi-pxa2xx.h | |
| parent | 4fdb2424cc4499237197a8c9d35b34d68c750475 (diff) | |
spi: spi-pxa2xx: SPI support for Intel Quark X1000
There are two SPI controllers exported by PCI subsystem for Intel Quark X1000.
The SPI memory mapped I/O registers supported by Quark are different from
the current implementation, and Quark only supports the registers of 'SSCR0',
'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable the SPI for
Intel Quark X1000.
This piece of work is derived from Dan O'Donovan's initial work for Intel Quark
X1000 SPI enabling.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Weike Chen <alvin.chen@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.h')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index 5adc2a11c7bc..6bec59c90cd4 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -93,6 +93,7 @@ struct driver_data { struct chip_data { u32 cr0; u32 cr1; + u32 dds_rate; u32 psp; u32 timeout; u8 n_bytes; @@ -126,6 +127,7 @@ DEFINE_SSP_REG(SSCR1, 0x04) DEFINE_SSP_REG(SSSR, 0x08) DEFINE_SSP_REG(SSITR, 0x0c) DEFINE_SSP_REG(SSDR, 0x10) +DEFINE_SSP_REG(DDS_RATE, 0x28) /* DDS Clock Rate */ DEFINE_SSP_REG(SSTO, 0x28) DEFINE_SSP_REG(SSPSP, 0x2c) DEFINE_SSP_REG(SSITF, SSITF) @@ -141,18 +143,22 @@ DEFINE_SSP_REG(SSIRF, SSIRF) static inline int pxa25x_ssp_comp(struct driver_data *drv_data) { - if (drv_data->ssp_type == PXA25x_SSP) + switch (drv_data->ssp_type) { + case PXA25x_SSP: + case CE4100_SSP: + case QUARK_X1000_SSP: return 1; - if (drv_data->ssp_type == CE4100_SSP) - return 1; - return 0; + default: + return 0; + } } static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) { void __iomem *reg = drv_data->ioaddr; - if (drv_data->ssp_type == CE4100_SSP) + if (drv_data->ssp_type == CE4100_SSP || + drv_data->ssp_type == QUARK_X1000_SSP) val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; write_SSSR(val, reg); |