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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2018-07-26 19:59:05 +0300
committerLinus Walleij <linus.walleij@linaro.org>2018-07-30 00:01:42 +0200
commit17ac526824a8b5544bc2545c76f489e49c6593a2 (patch)
treea43a7544c27e9260120f007b3fcc7792c6006b52 /drivers/pinctrl
parent3c94d2d08a032d911bbe34f2edb24cb63a63644a (diff)
pinctrl: cannonlake: Fix community ordering for H variant
The driver was written based on an assumption that BIOS provides unordered communities in ACPI DSDT. Nevertheless, it seems that BIOS getting fixed before being provisioned to OxM:s. So does driver. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199911 Reported-by: Marc Landolt <2009@marclandolt.ch> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support") Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/intel/pinctrl-cannonlake.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index 71ad67b8fc35..fb1afe55bf53 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -444,12 +444,8 @@ static const struct intel_function cnlh_functions[] = {
static const struct intel_community cnlh_communities[] = {
CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
- /*
- * ACPI MMIO resources are returned in reverse order for
- * communities 3 and 4.
- */
- CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
- CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
+ CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
+ CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnlh_soc_data = {