Merge tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "No core changes this time. Just new driver code and improvements!

  New drivers:

   - New driver for the Broadcom BCM4908 SoC.

   - New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative
     of the Samsung Exynos pin control driver.

   - New driver for the Amlogic Meson S4 SoC.

   - New driver for the Sunplus SP7021 SoC.

   - New driver for the Microsemi Ocelot family ServalT SoC.

   - New subdriver for Intel Alder Lake-M SoC.

   - New subdriver for Intel Ice Lake-N SoC, including PCH support.

   - New subdriver for Renesas R8A779F0 SoC.

   - New subdriver for Mediatek MT8186 SoC.

   - New subdriver for NXP Freescale i.MX93 SoC.

   - New driver for Nuvoton WPCM450 SoC.

   - New driver for Qualcomm SC8280XP SoC.

  Improvements:

   - Wakeup support on Samsung Exynos850 and ExynosAutov9.

   - Serious and voluminous maintenance cleanup and refactoring in the
     Renesas drivers. Mainly sharing similar data between the different
     SoC subdrivers.

   - Qualcomm SM8450 EGPIO support.

   - Drive strength support on the Mediatek MT8195.

   - Add some missing groups and functions to the Ralink RT2880"

* tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits)
  pinctrl: mediatek: common-v1: fix semicolon.cocci warnings
  pinctrl: nuvoton: wpcm450: Fix build error without OF
  pinctrl: qcom-pmic-gpio: Add support for pm8450
  dt-bindings: pinctrl: aspeed: Update gfx node in example
  dt-bindings: pinctrl: rt2880: add missing pin groups and functions
  pinctrl: ingenic: Fix regmap on X series SoCs
  pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register()
  pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register()
  pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS
  pinctrl: nuvoton: Fix sparse warning
  pinctrl: mediatek: mt8186: Account for probe refactoring
  pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback
  pinctrl: mediatek: common-v1: Commonize spec_pupd callback
  pinctrl: mediatek: common-v1: Use common probe function
  pinctrl: mediatek: common-v1: Add common probe function
  pinctrl: mediatek: paris: Unify probe function by using OF match data
  pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe
  pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe
  pinctrl: berlin: fix error return code of berlin_pinctrl_build_state()
  pinctrl: qcom: Introduce sc8280xp TLMM driver
  ...

3 files changed, 652 insertions, 11 deletions

diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c
index efb664f12b5d..32ba50efbceb 100644
--- a/drivers/pinctrl/intel/pinctrl-alderlake.c
+++ b/drivers/pinctrl/intel/pinctrl-alderlake.c
@@ -2,7 +2,7 @@
 /*
  * Intel Alder Lake PCH pinctrl/GPIO driver
  *
- * Copyright (C) 2020, Intel Corporation
+ * Copyright (C) 2020, 2022 Intel Corporation
  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  */
 
@@ -42,6 +42,319 @@
 		.ngpps = ARRAY_SIZE(g),			\
 	}
 
+/* Alder Lake-N */
+static const struct pinctrl_pin_desc adln_pins[] = {
+	/* GPP_B */
+	PINCTRL_PIN(0, "CORE_VID_0"),
+	PINCTRL_PIN(1, "CORE_VID_1"),
+	PINCTRL_PIN(2, "GPPC_B_2"),
+	PINCTRL_PIN(3, "GPPC_B_3"),
+	PINCTRL_PIN(4, "GPPC_B_4"),
+	PINCTRL_PIN(5, "GPPC_B_5"),
+	PINCTRL_PIN(6, "GPPC_B_6"),
+	PINCTRL_PIN(7, "GPPC_B_7"),
+	PINCTRL_PIN(8, "GPPC_B_8"),
+	PINCTRL_PIN(9, "GPPC_B_9"),
+	PINCTRL_PIN(10, "GPPC_B_10"),
+	PINCTRL_PIN(11, "GPPC_B_11"),
+	PINCTRL_PIN(12, "SLP_S0B"),
+	PINCTRL_PIN(13, "PLTRSTB"),
+	PINCTRL_PIN(14, "GPPC_B_14"),
+	PINCTRL_PIN(15, "GPPC_B_15"),
+	PINCTRL_PIN(16, "GPPC_B_16"),
+	PINCTRL_PIN(17, "GPPC_B_17"),
+	PINCTRL_PIN(18, "GPPC_B_18"),
+	PINCTRL_PIN(19, "GPPC_B_19"),
+	PINCTRL_PIN(20, "GPPC_B_20"),
+	PINCTRL_PIN(21, "GPPC_B_21"),
+	PINCTRL_PIN(22, "GPPC_B_22"),
+	PINCTRL_PIN(23, "GPPC_B_23"),
+	PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
+	PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
+	/* GPP_T */
+	PINCTRL_PIN(26, "GPPC_T_0"),
+	PINCTRL_PIN(27, "GPPC_T_1"),
+	PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"),
+	PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"),
+	PINCTRL_PIN(30, "GPPC_T_4"),
+	PINCTRL_PIN(31, "GPPC_T_5"),
+	PINCTRL_PIN(32, "GPPC_T_6"),
+	PINCTRL_PIN(33, "GPPC_T_7"),
+	PINCTRL_PIN(34, "GPPC_T_8"),
+	PINCTRL_PIN(35, "GPPC_T_9"),
+	PINCTRL_PIN(36, "GPPC_T_10"),
+	PINCTRL_PIN(37, "GPPC_T_11"),
+	PINCTRL_PIN(38, "GPPC_T_12"),
+	PINCTRL_PIN(39, "GPPC_T_13"),
+	PINCTRL_PIN(40, "GPPC_T_14"),
+	PINCTRL_PIN(41, "GPPC_T_15"),
+	/* GPP_A */
+	PINCTRL_PIN(42, "ESPI_IO_0"),
+	PINCTRL_PIN(43, "ESPI_IO_1"),
+	PINCTRL_PIN(44, "ESPI_IO_2"),
+	PINCTRL_PIN(45, "ESPI_IO_3"),
+	PINCTRL_PIN(46, "ESPI_CS0B"),
+	PINCTRL_PIN(47, "ESPI_ALERT0B"),
+	PINCTRL_PIN(48, "ESPI_ALERT1B"),
+	PINCTRL_PIN(49, "GPPC_A_7"),
+	PINCTRL_PIN(50, "GPPC_A_8"),
+	PINCTRL_PIN(51, "ESPI_CLK"),
+	PINCTRL_PIN(52, "ESPI_RESETB"),
+	PINCTRL_PIN(53, "GPPC_A_11"),
+	PINCTRL_PIN(54, "GPPC_A_12"),
+	PINCTRL_PIN(55, "GPPC_A_13"),
+	PINCTRL_PIN(56, "GPPC_A_14"),
+	PINCTRL_PIN(57, "GPPC_A_15"),
+	PINCTRL_PIN(58, "GPPC_A_16"),
+	PINCTRL_PIN(59, "GPPC_A_17"),
+	PINCTRL_PIN(60, "GPPC_A_18"),
+	PINCTRL_PIN(61, "GPPC_A_19"),
+	PINCTRL_PIN(62, "GPPC_A_20"),
+	PINCTRL_PIN(63, "GPPC_A_21"),
+	PINCTRL_PIN(64, "GPPC_A_22"),
+	PINCTRL_PIN(65, "ESPI_CS1B"),
+	PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
+	/* GPP_S */
+	PINCTRL_PIN(67, "GPP_S_0"),
+	PINCTRL_PIN(68, "GPP_S_1"),
+	PINCTRL_PIN(69, "GPP_S_2"),
+	PINCTRL_PIN(70, "GPP_S_3"),
+	PINCTRL_PIN(71, "GPP_S_4"),
+	PINCTRL_PIN(72, "GPP_S_5"),
+	PINCTRL_PIN(73, "GPP_S_6"),
+	PINCTRL_PIN(74, "GPP_S_7"),
+	/* GPP_I */
+	PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"),
+	PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"),
+	PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"),
+	PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"),
+	PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"),
+	PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"),
+	PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"),
+	PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"),
+	PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"),
+	PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"),
+	PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"),
+	PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"),
+	PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"),
+	PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"),
+	PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"),
+	PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"),
+	PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"),
+	PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"),
+	PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"),
+	PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"),
+	/* GPP_H */
+	PINCTRL_PIN(95, "GPPC_H_0"),
+	PINCTRL_PIN(96, "GPPC_H_1"),
+	PINCTRL_PIN(97, "GPPC_H_2"),
+	PINCTRL_PIN(98, "GPPC_H_3"),
+	PINCTRL_PIN(99, "GPPC_H_4"),
+	PINCTRL_PIN(100, "GPPC_H_5"),
+	PINCTRL_PIN(101, "GPPC_H_6"),
+	PINCTRL_PIN(102, "GPPC_H_7"),
+	PINCTRL_PIN(103, "GPPC_H_8"),
+	PINCTRL_PIN(104, "GPPC_H_9"),
+	PINCTRL_PIN(105, "GPPC_H_10"),
+	PINCTRL_PIN(106, "GPPC_H_11"),
+	PINCTRL_PIN(107, "I2C7_SDA"),
+	PINCTRL_PIN(108, "I2C7_SCL"),
+	PINCTRL_PIN(109, "GPPC_H_14"),
+	PINCTRL_PIN(110, "GPPC_H_15"),
+	PINCTRL_PIN(111, "GPPC_H_16"),
+	PINCTRL_PIN(112, "GPPC_H_17"),
+	PINCTRL_PIN(113, "CPU_C10_GATEB"),
+	PINCTRL_PIN(114, "GPPC_H_19"),
+	PINCTRL_PIN(115, "GPPC_H_20"),
+	PINCTRL_PIN(116, "GPPC_H_21"),
+	PINCTRL_PIN(117, "GPPC_H_22"),
+	PINCTRL_PIN(118, "GPPC_H_23"),
+	/* GPP_D */
+	PINCTRL_PIN(119, "GPPC_D_0"),
+	PINCTRL_PIN(120, "GPPC_D_1"),
+	PINCTRL_PIN(121, "GPPC_D_2"),
+	PINCTRL_PIN(122, "GPPC_D_3"),
+	PINCTRL_PIN(123, "GPPC_D_4"),
+	PINCTRL_PIN(124, "GPPC_D_5"),
+	PINCTRL_PIN(125, "GPPC_D_6"),
+	PINCTRL_PIN(126, "GPPC_D_7"),
+	PINCTRL_PIN(127, "GPPC_D_8"),
+	PINCTRL_PIN(128, "BSSB_LS2_RX"),
+	PINCTRL_PIN(129, "BSSB_LS2_TX"),
+	PINCTRL_PIN(130, "BSSB_LS3_RX"),
+	PINCTRL_PIN(131, "BSSB_LS3_TX"),
+	PINCTRL_PIN(132, "GPPC_D_13"),
+	PINCTRL_PIN(133, "GPPC_D_14"),
+	PINCTRL_PIN(134, "GPPC_D_15"),
+	PINCTRL_PIN(135, "GPPC_D_16"),
+	PINCTRL_PIN(136, "GPPC_D_17"),
+	PINCTRL_PIN(137, "GPPC_D_18"),
+	PINCTRL_PIN(138, "GPPC_D_19"),
+	PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"),
+	/* vGPIO */
+	PINCTRL_PIN(140, "CNV_BTEN"),
+	PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"),
+	PINCTRL_PIN(142, "CNV_BT_IF_SELECT"),
+	PINCTRL_PIN(143, "vCNV_BT_UART_TXD"),
+	PINCTRL_PIN(144, "vCNV_BT_UART_RXD"),
+	PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"),
+	PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"),
+	PINCTRL_PIN(147, "vCNV_MFUART1_TXD"),
+	PINCTRL_PIN(148, "vCNV_MFUART1_RXD"),
+	PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"),
+	PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"),
+	PINCTRL_PIN(151, "vUART0_TXD"),
+	PINCTRL_PIN(152, "vUART0_RXD"),
+	PINCTRL_PIN(153, "vUART0_CTS_B"),
+	PINCTRL_PIN(154, "vUART0_RTS_B"),
+	PINCTRL_PIN(155, "vISH_UART0_TXD"),
+	PINCTRL_PIN(156, "vISH_UART0_RXD"),
+	PINCTRL_PIN(157, "vISH_UART0_CTS_B"),
+	PINCTRL_PIN(158, "vISH_UART0_RTS_B"),
+	PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"),
+	PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"),
+	PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"),
+	PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"),
+	PINCTRL_PIN(163, "vI2S2_SCLK"),
+	PINCTRL_PIN(164, "vI2S2_SFRM"),
+	PINCTRL_PIN(165, "vI2S2_TXD"),
+	PINCTRL_PIN(166, "vI2S2_RXD"),
+	PINCTRL_PIN(167, "THC0_WOT_INT"),
+	PINCTRL_PIN(168, "THC1_WOT_INT"),
+	/* GPP_C */
+	PINCTRL_PIN(169, "SMBCLK"),
+	PINCTRL_PIN(170, "SMBDATA"),
+	PINCTRL_PIN(171, "SMBALERTB"),
+	PINCTRL_PIN(172, "SML0CLK"),
+	PINCTRL_PIN(173, "SML0DATA"),
+	PINCTRL_PIN(174, "GPPC_C_5"),
+	PINCTRL_PIN(175, "GPPC_C_6"),
+	PINCTRL_PIN(176, "GPPC_C_7"),
+	PINCTRL_PIN(177, "GPPC_C_8"),
+	PINCTRL_PIN(178, "GPPC_C_9"),
+	PINCTRL_PIN(179, "GPPC_C_10"),
+	PINCTRL_PIN(180, "GPPC_C_11"),
+	PINCTRL_PIN(181, "GPPC_C_12"),
+	PINCTRL_PIN(182, "GPPC_C_13"),
+	PINCTRL_PIN(183, "GPPC_C_14"),
+	PINCTRL_PIN(184, "GPPC_C_15"),
+	PINCTRL_PIN(185, "GPPC_C_16"),
+	PINCTRL_PIN(186, "GPPC_C_17"),
+	PINCTRL_PIN(187, "GPPC_C_18"),
+	PINCTRL_PIN(188, "GPPC_C_19"),
+	PINCTRL_PIN(189, "GPPC_C_20"),
+	PINCTRL_PIN(190, "GPPC_C_21"),
+	PINCTRL_PIN(191, "GPPC_C_22"),
+	PINCTRL_PIN(192, "GPPC_C_23"),
+	/* GPP_F */
+	PINCTRL_PIN(193, "CNV_BRI_DT"),
+	PINCTRL_PIN(194, "CNV_BRI_RSP"),
+	PINCTRL_PIN(195, "CNV_RGI_DT"),
+	PINCTRL_PIN(196, "CNV_RGI_RSP"),
+	PINCTRL_PIN(197, "CNV_RF_RESET_B"),
+	PINCTRL_PIN(198, "MODEM_CLKREQ"),
+	PINCTRL_PIN(199, "GPPC_F_6"),
+	PINCTRL_PIN(200, "GPPC_F_7"),
+	PINCTRL_PIN(201, "GPPC_F_8"),
+	PINCTRL_PIN(202, "BOOTMPC"),
+	PINCTRL_PIN(203, "GPPC_F_10"),
+	PINCTRL_PIN(204, "GPPC_F_11"),
+	PINCTRL_PIN(205, "GPPC_F_12"),
+	PINCTRL_PIN(206, "GPPC_F_13"),
+	PINCTRL_PIN(207, "GPPC_F_14"),
+	PINCTRL_PIN(208, "GPPC_F_15"),
+	PINCTRL_PIN(209, "GPPC_F_16"),
+	PINCTRL_PIN(210, "GPPC_F_17"),
+	PINCTRL_PIN(211, "GPPC_F_18"),
+	PINCTRL_PIN(212, "GPPC_F_19"),
+	PINCTRL_PIN(213, "EXT_PWR_GATEB"),
+	PINCTRL_PIN(214, "EXT_PWR_GATE2B"),
+	PINCTRL_PIN(215, "GPPC_F_22"),
+	PINCTRL_PIN(216, "GPPC_F_23"),
+	PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"),
+	/* HVCMOS */
+	PINCTRL_PIN(218, "L_BKLTEN"),
+	PINCTRL_PIN(219, "L_BKLTCTL"),
+	PINCTRL_PIN(220, "L_VDDEN"),
+	PINCTRL_PIN(221, "SYS_PWROK"),
+	PINCTRL_PIN(222, "SYS_RESETB"),
+	PINCTRL_PIN(223, "MLK_RSTB"),
+	/* GPP_E */
+	PINCTRL_PIN(224, "GPPC_E_0"),
+	PINCTRL_PIN(225, "GPPC_E_1"),
+	PINCTRL_PIN(226, "GPPC_E_2"),
+	PINCTRL_PIN(227, "GPPC_E_3"),
+	PINCTRL_PIN(228, "GPPC_E_4"),
+	PINCTRL_PIN(229, "GPPC_E_5"),
+	PINCTRL_PIN(230, "GPPC_E_6"),
+	PINCTRL_PIN(231, "GPPC_E_7"),
+	PINCTRL_PIN(232, "GPPC_E_8"),
+	PINCTRL_PIN(233, "GPPC_E_9"),
+	PINCTRL_PIN(234, "GPPC_E_10"),
+	PINCTRL_PIN(235, "GPPC_E_11"),
+	PINCTRL_PIN(236, "GPPC_E_12"),
+	PINCTRL_PIN(237, "GPPC_E_13"),
+	PINCTRL_PIN(238, "GPPC_E_14"),
+	PINCTRL_PIN(239, "FIVR_DIGPB_0"),
+	PINCTRL_PIN(240, "FIVR_DIGPB_1"),
+	PINCTRL_PIN(241, "GPPC_E_17"),
+	PINCTRL_PIN(242, "BSSB_LS0_RX"),
+	PINCTRL_PIN(243, "BSSB_LS0_TX"),
+	PINCTRL_PIN(244, "BSSB_LS1_RX"),
+	PINCTRL_PIN(245, "BSSB_LS1_TX"),
+	PINCTRL_PIN(246, "DNX_FORCE_RELOAD"),
+	PINCTRL_PIN(247, "GPPC_E_23"),
+	PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"),
+	/* GPP_R */
+	PINCTRL_PIN(249, "HDA_BCLK"),
+	PINCTRL_PIN(250, "HDA_SYNC"),
+	PINCTRL_PIN(251, "HDA_SDO"),
+	PINCTRL_PIN(252, "HDA_SDI_0"),
+	PINCTRL_PIN(253, "HDA_RSTB"),
+	PINCTRL_PIN(254, "GPP_R_5"),
+	PINCTRL_PIN(255, "GPP_R_6"),
+	PINCTRL_PIN(256, "GPP_R_7"),
+};
+
+static const struct intel_padgroup adln_community0_gpps[] = {
+	ADL_GPP(0, 0, 25, 0),				/* GPP_B */
+	ADL_GPP(1, 26, 41, 32),				/* GPP_T */
+	ADL_GPP(2, 42, 66, 64),				/* GPP_A */
+};
+
+static const struct intel_padgroup adln_community1_gpps[] = {
+	ADL_GPP(0, 67, 74, 96),				/* GPP_S */
+	ADL_GPP(1, 75, 94, 128),			/* GPP_I */
+	ADL_GPP(2, 95, 118, 160),			/* GPP_H */
+	ADL_GPP(3, 119, 139, 192),			/* GPP_D */
+	ADL_GPP(4, 140, 168, 224),			/* vGPIO */
+};
+
+static const struct intel_padgroup adln_community4_gpps[] = {
+	ADL_GPP(0, 169, 192, 256),			/* GPP_C */
+	ADL_GPP(1, 193, 217, 288),			/* GPP_F */
+	ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
+	ADL_GPP(3, 224, 248, 320),			/* GPP_E */
+};
+
+static const struct intel_padgroup adln_community5_gpps[] = {
+	ADL_GPP(0, 249, 256, 352),			/* GPP_R */
+};
+
+static const struct intel_community adln_communities[] = {
+	ADL_COMMUNITY(0, 0, 66, adln_community0_gpps),
+	ADL_COMMUNITY(1, 67, 168, adln_community1_gpps),
+	ADL_COMMUNITY(2, 169, 248, adln_community4_gpps),
+	ADL_COMMUNITY(3, 249, 256, adln_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data adln_soc_data = {
+	.pins = adln_pins,
+	.npins = ARRAY_SIZE(adln_pins),
+	.communities = adln_communities,
+	.ncommunities = ARRAY_SIZE(adln_communities),
+};
+
 /* Alder Lake-S */
 static const struct pinctrl_pin_desc adls_pins[] = {
 	/* GPP_I */
@@ -416,6 +729,8 @@ static const struct intel_pinctrl_soc_data adls_soc_data = {
 
 static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
 	{ "INTC1056", (kernel_ulong_t)&adls_soc_data },
+	{ "INTC1057", (kernel_ulong_t)&adln_soc_data },
+	{ "INTC1085", (kernel_ulong_t)&adls_soc_data },
 	{ }
 };
 MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 1cc660e6458e..f89c9fcd4e1b 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -32,6 +32,7 @@
 #define BYT_VAL_REG		0x008
 #define BYT_DFT_REG		0x00c
 #define BYT_INT_STAT_REG	0x800
+#define BYT_DIRECT_IRQ_REG	0x980
 #define BYT_DEBOUNCE_REG	0x9d0
 
 /* BYT_CONF0_REG register bits */
@@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
 	chip->irq_eoi(data);
 }
 
+static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
+{
+	int direct_irq, ioapic_direct_irq_base;
+	u8 *match, direct_irq_mux[16];
+	u32 trig;
+
+	memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
+		      sizeof(direct_irq_mux));
+	match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
+	if (!match) {
+		dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
+		return false;
+	}
+
+	direct_irq = match - direct_irq_mux;
+	/* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
+	ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
+	dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
+		direct_irq, direct_irq + ioapic_direct_irq_base);
+
+	/*
+	 * Testing has shown that the way direct IRQs work is that the combination of the
+	 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
+	 * trigger block, which normally sets the status flag in the IRQ status reg at
+	 * 0x800, to one of the IO-APIC pins according to the mux registers.
+	 *
+	 * This means that:
+	 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
+	 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
+	 *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
+	 *    selecting edge mode operation then on the first edge the IO-APIC pin goes
+	 *    high, but since no write-to-clear write will be done to the IRQ status reg
+	 *    at 0x800, the detected edge condition will never get cleared.
+	 */
+	trig = conf0 & BYT_TRIG_MASK;
+	if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
+	    trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
+		dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
+			 pin, conf0);
+		return false;
+	}
+
+	return true;
+}
+
 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
 				    unsigned long *valid_mask,
 				    unsigned int ngpios)
@@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
 
 		value = readl(reg);
 		if (value & BYT_DIRECT_IRQ_EN) {
-			clear_bit(i, valid_mask);
-			dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
+			if (byt_direct_irq_sanity_check(vg, i, value)) {
+				clear_bit(i, valid_mask);
+			} else {
+				value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
+					   BYT_TRIG_NEG | BYT_TRIG_LVL);
+				writel(value, reg);
+			}
 		} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
 			byt_gpio_clear_triggering(vg, i);
 			dev_dbg(vg->dev, "disabling GPIO %d\n", i);
diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c
index 429b5a83acf0..27c248cc16f7 100644
--- a/drivers/pinctrl/intel/pinctrl-icelake.c
+++ b/drivers/pinctrl/intel/pinctrl-icelake.c
@@ -2,7 +2,7 @@
 /*
  * Intel Ice Lake PCH pinctrl/GPIO driver
  *
- * Copyright (C) 2018, Intel Corporation
+ * Copyright (C) 2018, 2022 Intel Corporation
  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  *	    Mika Westerberg <mika.westerberg@linux.intel.com>
  */
@@ -19,7 +19,8 @@
 #define ICL_PADCFGLOCK	0x080
 #define ICL_HOSTSW_OWN	0x0b0
 #define ICL_GPI_IS	0x100
-#define ICL_GPI_IE	0x110
+#define ICL_LP_GPI_IE	0x110
+#define ICL_N_GPI_IE	0x120
 
 #define ICL_GPP(r, s, e, g)				\
 	{						\
@@ -29,20 +30,26 @@
 		.gpio_base = (g),			\
 	}
 
-#define ICL_COMMUNITY(b, s, e, g)			\
+#define ICL_COMMUNITY(b, s, e, ie, g)			\
 	{						\
 		.barno = (b),				\
 		.padown_offset = ICL_PAD_OWN,		\
 		.padcfglock_offset = ICL_PADCFGLOCK,	\
 		.hostown_offset = ICL_HOSTSW_OWN,	\
 		.is_offset = ICL_GPI_IS,		\
-		.ie_offset = ICL_GPI_IE,		\
+		.ie_offset = (ie),			\
 		.pin_base = (s),			\
 		.npins = ((e) - (s) + 1),		\
 		.gpps = (g),				\
 		.ngpps = ARRAY_SIZE(g),			\
 	}
 
+#define ICL_LP_COMMUNITY(b, s, e, g)			\
+	ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)
+
+#define ICL_N_COMMUNITY(b, s, e, g)			\
+	ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)
+
 /* Ice Lake-LP */
 static const struct pinctrl_pin_desc icllp_pins[] = {
 	/* GPP_G */
@@ -329,10 +336,10 @@ static const struct intel_padgroup icllp_community5_gpps[] = {
 };
 
 static const struct intel_community icllp_communities[] = {
-	ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
-	ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
-	ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
-	ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
+	ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
+	ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
+	ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
+	ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
 };
 
 static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
@@ -403,10 +410,278 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = {
 	.ncommunities = ARRAY_SIZE(icllp_communities),
 };
 
+/* Ice Lake-N */
+static const struct pinctrl_pin_desc icln_pins[] = {
+	/* SPI */
+	PINCTRL_PIN(0, "SPI0_IO_2"),
+	PINCTRL_PIN(1, "SPI0_IO_3"),
+	PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
+	PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
+	PINCTRL_PIN(4, "SPI0_TPM_CSB"),
+	PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
+	PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
+	PINCTRL_PIN(7, "SPI0_CLK"),
+	PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
+	/* GPP_B */
+	PINCTRL_PIN(9, "CORE_VID_0"),
+	PINCTRL_PIN(10, "CORE_VID_1"),
+	PINCTRL_PIN(11, "VRALERTB"),
+	PINCTRL_PIN(12, "CPU_GP_2"),
+	PINCTRL_PIN(13, "CPU_GP_3"),
+	PINCTRL_PIN(14, "SRCCLKREQB_0"),
+	PINCTRL_PIN(15, "SRCCLKREQB_1"),
+	PINCTRL_PIN(16, "SRCCLKREQB_2"),
+	PINCTRL_PIN(17, "SRCCLKREQB_3"),
+	PINCTRL_PIN(18, "SRCCLKREQB_4"),
+	PINCTRL_PIN(19, "SRCCLKREQB_5"),
+	PINCTRL_PIN(20, "EXT_PWR_GATEB"),
+	PINCTRL_PIN(21, "SLP_S0B"),
+	PINCTRL_PIN(22, "PLTRSTB"),
+	PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
+	PINCTRL_PIN(24, "GSPI0_CS0B"),
+	PINCTRL_PIN(25, "GSPI0_CLK"),
+	PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
+	PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
+	PINCTRL_PIN(28, "GSPI1_CS0B"),
+	PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
+	PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
+	PINCTRL_PIN(31, "GSPI1_MOSI"),
+	PINCTRL_PIN(32, "GSPI1_CS1B"),
+	PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
+	PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
+	/* GPP_A */
+	PINCTRL_PIN(35, "ESPI_IO_0"),
+	PINCTRL_PIN(36, "ESPI_IO_1"),
+	PINCTRL_PIN(37, "ESPI_IO_2"),
+	PINCTRL_PIN(38, "ESPI_IO_3"),
+	PINCTRL_PIN(39, "ESPI_CSB"),
+	PINCTRL_PIN(40, "ESPI_CLK"),
+	PINCTRL_PIN(41, "ESPI_RESETB"),
+	PINCTRL_PIN(42, "SMBCLK"),
+	PINCTRL_PIN(43, "SMBDATA"),
+	PINCTRL_PIN(44, "SMBALERTB"),
+	PINCTRL_PIN(45, "CPU_GP_0"),
+	PINCTRL_PIN(46, "CPU_GP_1"),
+	PINCTRL_PIN(47, "USB2_OCB_1"),
+	PINCTRL_PIN(48, "USB2_OCB_2"),
+	PINCTRL_PIN(49, "USB2_OCB_3"),
+	PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
+	PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
+	PINCTRL_PIN(52, "DDSP_HPD_C"),
+	PINCTRL_PIN(53, "USB2_OCB_0"),
+	PINCTRL_PIN(54, "PCHHOTB"),
+	PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
+	/* GPP_S */
+	PINCTRL_PIN(56, "SNDW1_CLK"),
+	PINCTRL_PIN(57, "SNDW1_DATA"),
+	PINCTRL_PIN(58, "SNDW2_CLK"),
+	PINCTRL_PIN(59, "SNDW2_DATA"),
+	PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
+	PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
+	PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
+	PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
+	/* GPP_R */
+	PINCTRL_PIN(64, "HDA_BCLK"),
+	PINCTRL_PIN(65, "HDA_SYNC"),
+	PINCTRL_PIN(66, "HDA_SDO"),
+	PINCTRL_PIN(67, "HDA_SDI_0"),
+	PINCTRL_PIN(68, "HDA_RSTB"),
+	PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
+	PINCTRL_PIN(70, "I2S1_SFRM"),
+	PINCTRL_PIN(71, "I2S1_TXD"),
+	/* GPP_H */
+	PINCTRL_PIN(72, "GPPC_H_0"),
+	PINCTRL_PIN(73, "CNV_RF_RESET_B"),
+	PINCTRL_PIN(74, "MODEM_CLKREQ"),
+	PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
+	PINCTRL_PIN(76, "I2C2_SDA"),
+	PINCTRL_PIN(77, "I2C2_SCL"),
+	PINCTRL_PIN(78, "I2C3_SDA"),
+	PINCTRL_PIN(79, "I2C3_SCL"),
+	PINCTRL_PIN(80, "I2C4_SDA"),
+	PINCTRL_PIN(81, "I2C4_SCL"),
+	PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
+	PINCTRL_PIN(83, "I2S2_SCLK"),
+	PINCTRL_PIN(84, "CNV_RF_RESET_B"),
+	PINCTRL_PIN(85, "MODEM_CLKREQ"),
+	PINCTRL_PIN(86, "I2S2_RXD"),
+	PINCTRL_PIN(87, "I2S1_SCLK"),
+	PINCTRL_PIN(88, "GPPC_H_16"),
+	PINCTRL_PIN(89, "GPPC_H_17"),
+	PINCTRL_PIN(90, "GPPC_H_18"),
+	PINCTRL_PIN(91, "GPPC_H_19"),
+	PINCTRL_PIN(92, "GPPC_H_20"),
+	PINCTRL_PIN(93, "GPPC_H_21"),
+	PINCTRL_PIN(94, "GPPC_H_22"),
+	PINCTRL_PIN(95, "GPPC_H_23"),
+	/* GPP_D */
+	PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
+	PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
+	PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
+	PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
+	PINCTRL_PIN(100, "ISH_I2C0_SDA"),
+	PINCTRL_PIN(101, "ISH_I2C0_SCL"),
+	PINCTRL_PIN(102, "ISH_I2C1_SDA"),
+	PINCTRL_PIN(103, "ISH_I2C1_SCL"),
+	PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
+	PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
+	PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
+	PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
+	PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
+	PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
+	PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
+	PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
+	PINCTRL_PIN(112, "SPI1_IO_2"),
+	PINCTRL_PIN(113, "SPI1_IO_3"),
+	PINCTRL_PIN(114, "I2S_MCLK"),
+	PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
+	PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
+	PINCTRL_PIN(117, "CNV_PA_BLANKING"),
+	PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
+	PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
+	PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
+	PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
+	/* vGPIO */
+	PINCTRL_PIN(122, "CNV_BTEN"),
+	PINCTRL_PIN(123, "CNV_WCEN"),
+	PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
+	PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
+	PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
+	PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
+	PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
+	PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
+	PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
+	PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
+	PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
+	PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
+	PINCTRL_PIN(134, "vUART0_TXD"),
+	PINCTRL_PIN(135, "vUART0_RXD"),
+	PINCTRL_PIN(136, "vUART0_CTS_B"),
+	PINCTRL_PIN(137, "vUART0_RTS_B"),
+	PINCTRL_PIN(138, "vISH_UART0_TXD"),
+	PINCTRL_PIN(139, "vISH_UART0_RXD"),
+	PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
+	PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
+	PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
+	PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
+	PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
+	PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
+	PINCTRL_PIN(146, "vI2S2_SCLK"),
+	PINCTRL_PIN(147, "vI2S2_SFRM"),
+	PINCTRL_PIN(148, "vI2S2_TXD"),
+	PINCTRL_PIN(149, "vI2S2_RXD"),
+	PINCTRL_PIN(150, "vSD3_CD_B"),
+	/* GPP_C */
+	PINCTRL_PIN(151, "GPPC_C_0"),
+	PINCTRL_PIN(152, "GPPC_C_1"),
+	PINCTRL_PIN(153, "GPPC_C_2"),
+	PINCTRL_PIN(154, "GPPC_C_3"),
+	PINCTRL_PIN(155, "GPPC_C_4"),
+	PINCTRL_PIN(156, "GPPC_C_5"),
+	PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
+	PINCTRL_PIN(158, "SUSACKB"),
+	PINCTRL_PIN(159, "UART0_RXD"),
+	PINCTRL_PIN(160, "UART0_TXD"),
+	PINCTRL_PIN(161, "UART0_RTSB"),
+	PINCTRL_PIN(162, "UART0_CTSB"),
+	PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
+	PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
+	PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
+	PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
+	PINCTRL_PIN(167, "I2C0_SDA"),
+	PINCTRL_PIN(168, "I2C0_SCL"),
+	PINCTRL_PIN(169, "I2C1_SDA"),
+	PINCTRL_PIN(170, "I2C1_SCL"),
+	PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
+	PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
+	PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
+	PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
+	/* HVCMOS */
+	PINCTRL_PIN(175, "L_BKLTEN"),
+	PINCTRL_PIN(176, "L_BKLTCTL"),
+	PINCTRL_PIN(177, "L_VDDEN"),
+	PINCTRL_PIN(178, "SYS_PWROK"),
+	PINCTRL_PIN(179, "SYS_RESETB"),
+	PINCTRL_PIN(180, "MLK_RSTB"),
+	/* GPP_E */
+	PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
+	PINCTRL_PIN(182, "ISH_GP_1"),
+	PINCTRL_PIN(183, "IMGCLKOUT_1"),
+	PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
+	PINCTRL_PIN(185, "IMGCLKOUT_2"),
+	PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
+	PINCTRL_PIN(187, "IMGCLKOUT_3"),
+	PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
+	PINCTRL_PIN(189, "FIVR_DIGPB_0"),
+	PINCTRL_PIN(190, "SML0CLK"),
+	PINCTRL_PIN(191, "SML0DATA"),
+	PINCTRL_PIN(192, "BSSB_LS3_RX"),
+	PINCTRL_PIN(193, "BSSB_LS3_TX"),
+	PINCTRL_PIN(194, "BSSB_LS0_RX"),
+	PINCTRL_PIN(195, "BSSB_LS0_TX"),
+	PINCTRL_PIN(196, "BSSB_LS1_RX"),
+	PINCTRL_PIN(197, "BSSB_LS1_TX"),
+	PINCTRL_PIN(198, "BSSB_LS2_RX"),
+	PINCTRL_PIN(199, "BSSB_LS2_TX"),
+	PINCTRL_PIN(200, "FIVR_DIGPB_1"),
+	PINCTRL_PIN(201, "CNV_BRI_DT"),
+	PINCTRL_PIN(202, "CNV_BRI_RSP"),
+	PINCTRL_PIN(203, "CNV_RGI_DT"),
+	PINCTRL_PIN(204, "CNV_RGI_RSP"),
+	/* GPP_G */
+	PINCTRL_PIN(205, "SD3_CMD"),
+	PINCTRL_PIN(206, "SD3_D0"),
+	PINCTRL_PIN(207, "SD3_D1"),
+	PINCTRL_PIN(208, "SD3_D2"),
+	PINCTRL_PIN(209, "SD3_D3"),
+	PINCTRL_PIN(210, "SD3_CDB"),
+	PINCTRL_PIN(211, "SD3_CLK"),
+	PINCTRL_PIN(212, "SD3_WP"),
+};
+
+static const struct intel_padgroup icln_community0_gpps[] = {
+	ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP),	/* SPI */
+	ICL_GPP(1, 9, 34, 32),				/* GPP_B */
+	ICL_GPP(2, 35, 55, 64),				/* GPP_A */
+	ICL_GPP(3, 56, 63, 96),				/* GPP_S */
+	ICL_GPP(4, 64, 71, 128),			/* GPP_R */
+};
+
+static const struct intel_padgroup icln_community1_gpps[] = {
+	ICL_GPP(0, 72, 95, 160),			/* GPP_H */
+	ICL_GPP(1, 96, 121, 192),			/* GPP_D */
+	ICL_GPP(2, 122, 150, 224),			/* vGPIO */
+	ICL_GPP(3, 151, 174, 256),			/* GPP_C */
+};
+
+static const struct intel_padgroup icln_community4_gpps[] = {
+	ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
+	ICL_GPP(1, 181, 204, 288),			/* GPP_E */
+};
+
+static const struct intel_padgroup icln_community5_gpps[] = {
+	ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO),	/* GPP_G */
+};
+
+static const struct intel_community icln_communities[] = {
+	ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
+	ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
+	ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
+	ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data icln_soc_data = {
+	.pins = icln_pins,
+	.npins = ARRAY_SIZE(icln_pins),
+	.communities = icln_communities,
+	.ncommunities = ARRAY_SIZE(icln_communities),
+};
+
 static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
 
 static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
 	{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
+	{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
 	{ }
 };
 MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);