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authorBjorn Helgaas <bhelgaas@google.com>2020-08-05 18:24:18 -0500
committerBjorn Helgaas <bhelgaas@google.com>2020-08-05 18:24:18 -0500
commit13a77336f4f5681068bbaa4eac3ba8adff684a54 (patch)
tree22ed45537c1789610c8acf77dfd9ccb4f3d4c070 /drivers/misc
parent5b17dbab263035aa1dc8e61637bc719f47c60daa (diff)
parent0dbe77c9d2f8e6ef1792db99e150dd0025a977eb (diff)
Merge branch 'remotes/lorenzo/pci/cadence'
- Convert cadence to use standard "dma-ranges" DT property instead of its own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I) - Fix pm_runtime_put_sync() issues in cadence error paths (Kishon Vijay Abraham I) - Add PTR_ALIGN_DOWN macro (Kishon Vijay Abraham I) - Convert cadence r/w accessors to only 32-bit accesses (Kishon Vijay Abraham I) - Add cadence support to start Link and check Link status (Kishon Vijay Abraham I) - Allow custom PCI ops for cadence-based drivers (Kishon Vijay Abraham I) - Remove "mem" from cadence reg binding since it's not memory and it overlaps the PCIe config and memory region (Kishon Vijay Abraham I) - Add cadence ->cpu_addr_fixup() for platforms that require absolute addresses in the ATU, not just offsets (Kishon Vijay Abraham I) - Update cadence Vendor IDs using local management registers, not architected config space (Kishon Vijay Abraham I) - Add cadence endpoint driver MSI-X support (Kishon Vijay Abraham I) - Add bindings and driver for TI J721E SoC, supporting both host and endpoint mode (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe misc: pci_endpoint_test: Add J721E in pci_device_id table PCI: j721e: Add TI J721E PCIe driver dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC PCI: cadence: Add MSI-X support to Endpoint driver PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register PCI: cadence: Add new *ops* for CPU addr fixup dt-bindings: PCI: cadence: Remove "mem" from reg binding PCI: cadence: Allow pci_host_bridge to have custom pci_ops PCI: cadence: Add support to start link and verify link status PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
Diffstat (limited to 'drivers/misc')
-rw-r--r--drivers/misc/pci_endpoint_test.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 41c40971979e..e060796f9caa 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -68,6 +68,7 @@
#define PCI_ENDPOINT_TEST_FLAGS 0x2c
#define FLAG_USE_DMA BIT(0)
+#define PCI_DEVICE_ID_TI_J721E 0xb00d
#define PCI_DEVICE_ID_TI_AM654 0xb00c
#define is_am654_pci_dev(pdev) \
@@ -932,6 +933,11 @@ static const struct pci_endpoint_test_data am654_data = {
.irq_type = IRQ_TYPE_MSI,
};
+static const struct pci_endpoint_test_data j721e_data = {
+ .alignment = 256,
+ .irq_type = IRQ_TYPE_MSI,
+};
+
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
.driver_data = (kernel_ulong_t)&default_data,
@@ -946,6 +952,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
},
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
+ .driver_data = (kernel_ulong_t)&j721e_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);