diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-05-08 18:56:31 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-14 11:53:16 +0100 |
| commit | 7d12a61187aed57863c41032acbc1fae516d6e49 (patch) | |
| tree | 8aabafa03bf14800ab99dba5d75689eb2f0c2062 /drivers/iio/dac | |
| parent | d0c167ceff2d833ee493dd58164dc87bd36e48aa (diff) | |
iio: dac: ad5761: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 131497acd88a ("iio: add ad5761 DAC driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-52-jic23@kernel.org
Diffstat (limited to 'drivers/iio/dac')
| -rw-r--r-- | drivers/iio/dac/ad5761.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c index 4cb8471db81e..6aa1a068adb0 100644 --- a/drivers/iio/dac/ad5761.c +++ b/drivers/iio/dac/ad5761.c @@ -70,13 +70,13 @@ struct ad5761_state { enum ad5761_voltage_range range; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[3] ____cacheline_aligned; + } data[3] __aligned(IIO_DMA_MINALIGN); }; static const struct ad5761_range_params ad5761_range_params[] = { |