diff options
author | Harsh Jain <harsh@chelsio.com> | 2018-10-13 13:46:56 +0530 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2018-10-17 14:16:19 +0800 |
commit | a1c6fd4308d37f072e939a2782f24214115fc7e8 (patch) | |
tree | 1ebe9aefa758a96a8b998f7001fd65f13c8d51fe /drivers/crypto | |
parent | 18e732b8035d175181aae2ded127994cb01694f7 (diff) |
crypto: chelsio - Update ntx queue received from cxgb4
Update cxgb4 to send No. of Tx Queue created in lldinfo struct
and use the same ntxq in chcr driver.
This patch depends on following commit
commit add92a817e60e308a419693413a38d9d1e663aff
"Fix memory corruption in DMA Mapped buffers"
v2:
Free txq_info in error case as pointed by Lino Sanfilippo.
Signed-off-by: Harsh Jain <harsh@chelsio.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
-rw-r--r-- | drivers/crypto/chelsio/chcr_algo.c | 3 | ||||
-rw-r--r-- | drivers/crypto/chelsio/chcr_core.c | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c index d5e4816b2d3e..db203f8be429 100644 --- a/drivers/crypto/chelsio/chcr_algo.c +++ b/drivers/crypto/chelsio/chcr_algo.c @@ -1338,8 +1338,7 @@ static int chcr_device_init(struct chcr_context *ctx) } ctx->dev = u_ctx->dev; adap = padap(ctx->dev); - ntxq = min_not_zero((unsigned int)u_ctx->lldi.nrxq, - adap->vres.ncrypto_fc); + ntxq = u_ctx->lldi.ntxq; rxq_perchan = u_ctx->lldi.nrxq / u_ctx->lldi.nchan; txq_perchan = ntxq / u_ctx->lldi.nchan; spin_lock(&ctx->dev->lock_chcr_dev); diff --git a/drivers/crypto/chelsio/chcr_core.c b/drivers/crypto/chelsio/chcr_core.c index 04f277cade7c..2399ce336a76 100644 --- a/drivers/crypto/chelsio/chcr_core.c +++ b/drivers/crypto/chelsio/chcr_core.c @@ -43,7 +43,7 @@ static chcr_handler_func work_handlers[NUM_CPL_CMDS] = { static struct cxgb4_uld_info chcr_uld_info = { .name = DRV_MODULE_NAME, .nrxq = MAX_ULD_QSETS, - .ntxq = MAX_ULD_QSETS, + /* Max ntxq will be derived from fw config file*/ .rxq_size = 1024, .add = chcr_uld_add, .state_change = chcr_uld_state_change, |