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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2021-12-28 07:54:06 +0300
committerBjorn Andersson <bjorn.andersson@linaro.org>2022-02-10 18:33:30 -0600
commitcf4cd3dcb79a14c95474389cd6eb6fd8c18a121b (patch)
treebf5a00ea9dd949eb3c0e84e708a57bcf5e084e98 /drivers/clk/qcom
parentf1697f36196e3aee1b7585610df494cef1a72393 (diff)
clk: qcom: camcc-sdm845: use ARRAY_SIZE instead of specifying num_parents
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211228045415.20543-8-dmitry.baryshkov@linaro.org
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r--drivers/clk/qcom/camcc-sdm845.c50
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 1b2cefef7431..97024e466dcd 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -190,7 +190,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -213,7 +213,7 @@ static struct clk_rcg2 cam_cc_cci_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -233,7 +233,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -254,7 +254,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -269,7 +269,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -284,7 +284,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -299,7 +299,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -324,7 +324,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -347,7 +347,7 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -370,7 +370,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -394,7 +394,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -417,7 +417,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -431,7 +431,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -446,7 +446,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -460,7 +460,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -475,7 +475,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -500,7 +500,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -515,7 +515,7 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -530,7 +530,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -555,7 +555,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -578,7 +578,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -593,7 +593,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -608,7 +608,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -623,7 +623,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
@@ -647,7 +647,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},