diff options
| author | Vinod Koul <vkoul@kernel.org> | 2021-01-27 12:38:08 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-02-08 10:03:57 -0800 |
| commit | 80ca7765fc75b3fcfa99bc9c1716bbb793c0b179 (patch) | |
| tree | 836e656c5b6cf4d6fc947027c4728f7e9915fe9a /drivers/clk/qcom/clk-alpha-pll.c | |
| parent | 160210b4833156f5dc6515e65f6eb4fec527fb62 (diff) | |
clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()
Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
with different registers. Modularize these by moving out latch and latch
ack bits so that we can reuse the function.
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127070811.152690-3-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/clk-alpha-pll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f7721088494c..a30ea7b09224 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1471,8 +1471,8 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); } -static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) +static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u32 latch_bit, u32 latch_ack) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; @@ -1490,22 +1490,20 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); /* Latch the PLL input */ - ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), - PLL_UPDATE, PLL_UPDATE); + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); if (ret) return ret; /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); - if (!(val & ALPHA_PLL_ACK_LATCH)) { + if (!(val & latch_ack)) { pr_err("Lucid PLL latch failed. Output may be unstable!\n"); return -EINVAL; } /* Return the latch input to 0 */ - ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), - PLL_UPDATE, 0); + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); if (ret) return ret; @@ -1520,6 +1518,12 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); +} + const struct clk_ops clk_alpha_pll_trion_ops = { .prepare = alpha_pll_trion_prepare, .enable = clk_trion_pll_enable, |