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authorAndrew Jeffery <andrew@aj.id.au>2019-10-10 12:36:55 +1030
committerStephen Boyd <sboyd@kernel.org>2019-11-26 10:02:48 -0800
commit801b787a693ba643b23608cf2bf8dcfab3608795 (patch)
tree4fe5be9b06248ae006cd17eebfde32c9cd5ec0a8 /drivers/clk/pxa
parent3696eebd810cf084b3662d3c3b85cd84b61090f3 (diff)
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
RCLK is a fixed 50MHz clock derived from HPLL that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20191010020655.3776-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/pxa')
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