diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2020-03-09 18:12:00 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-03-12 10:51:20 +0100 |
| commit | 9aa7dea8d66e05bbb331eb214327f7d1b82d00ad (patch) | |
| tree | 84d461bf2d81653e60b425d971392a2a9ef5f1d9 /arch | |
| parent | 5fc00fce6276cd8e9231586bdd3e5c4d44f8f9f7 (diff) | |
arm64: dts: renesas: r8a77990: Add CPUIdle support for CA53 cores
Enable cpuidle (core shutdown) support for the CA53 cores on R-Car E3.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200309171200.21226-1-geert+renesas@glider.be
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77990.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 0ad20b78e6eb..1543f18e834f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -88,6 +88,7 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <277>; clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; @@ -100,6 +101,7 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -110,6 +112,19 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; }; extal_clk: extal { |