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authorJoerg Roedel <jroedel@suse.de>2020-09-07 15:15:24 +0200
committerBorislav Petkov <bp@suse.de>2020-09-07 19:45:25 +0200
commit597cfe48212a3f110ab0f918bf59791f453e65b7 (patch)
tree3ca6f66974264437ac3d4c71f95b3a21e5d159b3 /arch/x86/boot/compressed/idt_handlers_64.S
parentc81d60029a1393183d2125fcb4b64831629b8864 (diff)
x86/boot/compressed/64: Setup a GHCB-based VC Exception handler
Install an exception handler for #VC exception that uses a GHCB. Also add the infrastructure for handling different exit-codes by decoding the instruction that caused the exception and error handling. Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200907131613.12703-24-joro@8bytes.org
Diffstat (limited to 'arch/x86/boot/compressed/idt_handlers_64.S')
-rw-r--r--arch/x86/boot/compressed/idt_handlers_64.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S
index 92eb4df478a1..22890e199f5b 100644
--- a/arch/x86/boot/compressed/idt_handlers_64.S
+++ b/arch/x86/boot/compressed/idt_handlers_64.S
@@ -72,5 +72,6 @@ SYM_FUNC_END(\name)
EXCEPTION_HANDLER boot_page_fault do_boot_page_fault error_code=1
#ifdef CONFIG_AMD_MEM_ENCRYPT
-EXCEPTION_HANDLER boot_stage1_vc do_vc_no_ghcb error_code=1
+EXCEPTION_HANDLER boot_stage1_vc do_vc_no_ghcb error_code=1
+EXCEPTION_HANDLER boot_stage2_vc do_boot_stage2_vc error_code=1
#endif