diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-01-19 11:18:19 +0100 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@st.com> | 2018-02-12 15:24:38 +0100 |
| commit | 1d91958fbe11d11a0c982e12616ed23f935852f1 (patch) | |
| tree | 32c267b78cf769b0f6766c3c74529e05d6b8e598 /arch/arm/boot/dts/stih418.dtsi | |
| parent | a388871750f63e93b26cc475bf8a64309dc95031 (diff) | |
ARM: dts: STi: Add fake reg property for usb2_picophyX nodes
Add fake reg property for usb2_picophy nodes.
This allows to fix the following warning when compiling dtb
with W=1 option :
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih418.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih418.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index e6525ab4d9bb..0efb3cd6a86e 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -30,8 +30,9 @@ }; soc { - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xf8 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -39,8 +40,9 @@ reset-names = "global", "port"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xfc 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, |