diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-24 22:10:59 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-24 22:10:59 -0500 |
| commit | 2e4c7588f6c1d24ae991a85140e05139e953c9b5 (patch) | |
| tree | 4630e475907f5f564d00f3453c27cf0c786bf7a0 /arch/arm/boot/dts/socfpga.dtsi | |
| parent | 7db85dd0828803f44f50ed6953f3f7cb762b830d (diff) | |
ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
The dbg_base_clk can also have osc1 has a parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 86e0fb6fff9c..01bdaaa50854 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -164,7 +164,7 @@ dbg_base_clk: dbg_base_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; + clocks = <&main_pll>, <&osc1>; div-reg = <0xe8 0 9>; reg = <0x50>; }; |