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authorTony Lindgren <tony@atomide.com>2022-02-04 09:33:32 +0200
committerTony Lindgren <tony@atomide.com>2022-04-11 16:03:32 +0300
commit9bc059f71c0ad5a1a9a94556a2e77fde6416fcec (patch)
tree44df4036637c8085d3668d7488f458b284ba9db1 /arch/arm/boot/dts/am33xx-clocks.dtsi
parent00950028d0796f2f130a6bb04903fe91b988b4e7 (diff)
ARM: dts: Add clksel node for am3 clkout
Let's add a clksel node for the component clocks to avoid devicetree unique_unit_address warnings. The component clocks can now get IO address from the parent clksel node. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <kristo@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Message-Id: <20220204073333.18175-4-tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am33xx-clocks.dtsi')
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi47
1 files changed, 27 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index a70ce9f3fb27..632147b16244 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -524,28 +524,35 @@
};
};
- sysclkout_pre_ck: sysclkout_pre_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
- reg = <0x0700>;
- };
+ clock@700 {
+ compatible = "ti,clksel";
+ reg = <0x700>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- clkout2_div_ck: clkout2_div_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sysclkout_pre_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <8>;
- reg = <0x0700>;
- };
+ sysclkout_pre_ck: clock-sysclkout-pre {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "sysclkout_pre_ck";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ };
- clkout2_ck: clkout2_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout2_div_ck>;
- ti,bit-shift = <7>;
- reg = <0x0700>;
+ clkout2_div_ck: clock-clkout2-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "clkout2_div_ck";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <8>;
+ };
+
+ clkout2_ck: clock-clkout2 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_ck";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ };
};
};