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authorVineet Gupta <vgupta@synopsys.com>2017-02-02 09:09:50 -0800
committerVineet Gupta <vgupta@synopsys.com>2017-02-06 09:37:57 -0800
commit8ba605b607b7278548c1092b2ac36381627f0839 (patch)
tree1fb4e234a793d0f579402f510bae8e00ee5a15f1 /arch/arc/Kconfig
parentb48fba057ca850d69cd8fde5adbbdf927206514b (diff)
ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant
A typical SMP system expects cache coherency. Initial NPS platform support was slated to be SMP w/o cache coherency. However it seems the platform now selects that option, so there is no point in keeping it around. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/Kconfig')
-rw-r--r--arch/arc/Kconfig6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index ba15cb8f60fb..c9f30f4763ab 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -180,16 +180,12 @@ config CPU_BIG_ENDIAN
config SMP
bool "Symmetric Multi-Processing"
default n
- select ARC_HAS_COH_CACHES if ISA_ARCV2
select ARC_MCIP if ISA_ARCV2
help
This enables support for systems with more than one CPU.
if SMP
-config ARC_HAS_COH_CACHES
- def_bool n
-
config NR_CPUS
int "Maximum number of CPUs (2-4096)"
range 2 4096
@@ -219,8 +215,6 @@ config ARC_MCIP
menuconfig ARC_CACHE
bool "Enable Cache Support"
default y
- # if SMP, cache enabled ONLY if ARC implementation has cache coherency
- depends on !SMP || ARC_HAS_COH_CACHES
if ARC_CACHE