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authorVineet Gupta <vgupta@synopsys.com>2016-09-29 10:00:14 -0700
committerVineet Gupta <vgupta@synopsys.com>2016-10-16 15:49:07 -0700
commit3ce0fefc51bd56381b1b9a92835cf8f9db3f2ef8 (patch)
treec425859767f89b65b4d11b41325632ffd82afffb /arch/arc/Kconfig
parent1001354ca34179f3db924eb66672442a173147dc (diff)
ARCv2: intc: untangle SMP, MCIP and IDU
The IDU intc is technically part of MCIP (Multi-core IP) hence historically was only available in a SMP hardware build (and thus only in a SMP kernel build). Now that hardware restriction has been lifted, so a UP kernel needs to support it. This requires breaking mcip.c into parts which are strictly SMP (inter-core interrupts) and IDU which in reality is just another intc and thus has no bearing on SMP. This change allows IDU in UP builds and with a suitable device tree, we can have the cascaded intc system ARCv2 core intc <---> ARCv2 IDU intc <---> periperals Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/Kconfig')
-rw-r--r--arch/arc/Kconfig17
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index ecd12379e2cd..6f67895cd9c4 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -186,14 +186,6 @@ if SMP
config ARC_HAS_COH_CACHES
def_bool n
-config ARC_MCIP
- bool "ARConnect Multicore IP (MCIP) Support "
- depends on ISA_ARCV2
- help
- This IP block enables SMP in ARC-HS38 cores.
- It provides for cross-core interrupts, multi-core debug
- hardware semaphores, shared memory,....
-
config NR_CPUS
int "Maximum number of CPUs (2-4096)"
range 2 4096
@@ -211,6 +203,15 @@ config ARC_SMP_HALT_ON_RESET
endif #SMP
+config ARC_MCIP
+ bool "ARConnect Multicore IP (MCIP) Support "
+ depends on ISA_ARCV2
+ default y if SMP
+ help
+ This IP block enables SMP in ARC-HS38 cores.
+ It provides for cross-core interrupts, multi-core debug
+ hardware semaphores, shared memory,....
+
menuconfig ARC_CACHE
bool "Enable Cache Support"
default y