diff options
| author | Mika Kahola <mika.kahola@intel.com> | 2023-12-19 14:32:46 +0200 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2024-01-04 12:54:32 +0200 |
| commit | a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5 (patch) | |
| tree | 38c959ed5ed3aca69ed4e1657181f737b44c8b15 | |
| parent | 2e13b5bb5e28a098eecd2b5f00d745b27f87e2e8 (diff) | |
drm/i915/display: Skip C10 state verification in case of fastset
PLL's are not programmed in case of fastset so the state
verification compares bios programmed PLL values against
sw PLL values. To overcome this limitation, we can skip
the state verification for C10 in fastset case as the
driver is not writing PLL values.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231219123246.832245-1-mika.kahola@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d0b6b4e439e1..ce1bddf74a82 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3009,6 +3009,9 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state, const struct intel_c10pll_state *mpllb_sw_state = &state->cx0pll_state.c10; int i; + if (intel_crtc_needs_fastset(state)) + return; + for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { u8 expected = mpllb_sw_state->pll[i]; |