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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2023-07-17 12:24:53 +0530
committerKrzysztof Wilczyński <kwilczynski@kernel.org>2023-08-25 17:33:18 +0000
commit8cd2b8ce48e52bfda76a04be9aef8c1b176693d9 (patch)
tree8a3b9fadbf48b21175721e93898e8950da8a6c8f
parent06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff)
PCI: qcom-ep: Pass alignment restriction to the EPF core
Qcom PCIe EP controllers have 4K alignment restriction for the outbound window address. Hence, pass this info to the EPF core so that the EPF drivers can make use of this info. Link: https://lore.kernel.org/linux-pci/20230717065459.14138-2-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
-rw-r--r--drivers/pci/controller/dwc/pcie-qcom-ep.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 0fe7f06f2102..736be5bee458 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -706,6 +706,7 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
.core_init_notifier = true,
.msi_capable = true,
.msix_capable = false,
+ .align = SZ_4K,
};
static const struct pci_epc_features *