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authorDamien Lespiau <damien.lespiau@intel.com>2014-07-29 18:06:20 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-07-30 13:21:18 +0200
commiteded9a08e20636b242455b0e841565a855ffa217 (patch)
tree284ef4c23b4e20590175516e11ff828d1ce95f51
parent9eaa4844e3b6210f4d0c2760e73218e19c9b6855 (diff)
drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDW
Future platform will use config->ddi_pll_sel in a different way. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9247d82f1dc2..8a33c08e16f9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -943,7 +943,7 @@ found:
&pipe_config->dp_m2_n2);
}
- if (HAS_DDI(dev))
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
else
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);