diff options
| author | Damien Lespiau <damien.lespiau@intel.com> | 2012-10-11 15:24:04 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-11 22:37:17 +0200 |
| commit | 39bc66c9371fa6cdb1029e6c1768824f068be913 (patch) | |
| tree | eec72949606ec43cab95f18c8504c5f4fdd937ac /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | 1ce4292073695fd0fec74d1169bc94dadc339731 (diff) | |
drm/i915: Fix the SCC/SSC typo in the SPLL bits definitiondrm-intel-next-2012-10-12
We're talking about Spread Spectrum Clocks here, thus SSC.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e79d0db4abf..a78860a04a5 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -814,7 +814,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) WARN(I915_READ(reg) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); - val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SCC; + val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; } else { WARN(1, "Invalid DDI encoder type %d\n", type); |