diff options
| author | David Mackey <tdmackey@twitter.com> | 2012-04-17 11:30:52 -0700 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2012-04-30 13:28:41 +0200 |
| commit | 15ed103a98008d85f20956e0e29c2cae78051efe (patch) | |
| tree | a1b38541e37863a2a978dde738bf3ec6a2d4ee9c /drivers/edac/edac_core.h | |
| parent | 90449e5dee4800721a352af11ae4d65d4a56ba93 (diff) | |
edac: Fix spelling errors.
Signed-off-by: David Mackey <tdmackey@twitter.com>
Signed-off-by: Vinson Lee <vlee@twitter.com>
Acked-by: Randy Dunlap <rdunlap@xenotime.net>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'drivers/edac/edac_core.h')
| -rw-r--r-- | drivers/edac/edac_core.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h index e48ab3108ad..841bb2d7ce6 100644 --- a/drivers/edac/edac_core.h +++ b/drivers/edac/edac_core.h @@ -107,13 +107,13 @@ extern int edac_debug_level; * * CPU caches (L1 and L2) * DMA engines - * Core CPU swithces + * Core CPU switches * Fabric switch units * PCIe interface controllers * other EDAC/ECC type devices that can be monitored for * errors, etc. * - * It allows for a 2 level set of hiearchry. For example: + * It allows for a 2 level set of hierarchy. For example: * * cache could be composed of L1, L2 and L3 levels of cache. * Each CPU core would have its own L1 cache, while sharing @@ -460,7 +460,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, /* * The no info errors are used when error overflows are reported. * There are a limited number of error logging registers that can - * be exausted. When all registers are exhausted and an additional + * be exhausted. When all registers are exhausted and an additional * error occurs then an error overflow register records that an * error occurred and the type of error, but doesn't have any * further information. The ce/ue versions make for cleaner |