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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-07 15:31:52 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-08 08:56:25 +0100
commitb05eddb8a7b138adf861771828a1a2f9658091b7 (patch)
treede4cfaec3eb3d956e5d0127ac1c08e7c932d28db
parent13288f454008724b4346dc1f8ca891849baee79d (diff)
drm/i915: Mask the vblank interrupt on bdw by defaultbdw-stage1-2013-11-08
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bf71e352fd7..1ce5722c246 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2917,15 +2917,15 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
- uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
- GEN8_PIPE_VBLANK |
- GEN8_PIPE_CDCLK_CRC_DONE |
- GEN8_PIPE_FIFO_UNDERRUN |
- GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+ uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
+ GEN8_PIPE_CDCLK_CRC_DONE |
+ GEN8_PIPE_FIFO_UNDERRUN |
+ GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+ uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
int pipe;
- dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
- dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
- dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;
+ dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
+ dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
+ dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
for_each_pipe(pipe) {
u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));