1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
|
x86info v1.11. Dave Jones 2001, 2002
Feedback to <davej@suse.de>.
Found 2 CPUs
MP Table:
# APIC ID Version State Family Model Step Flags
# 0 0x14 BSP, usable 15 2 7 0xbfebfbff
# 1 0x14 AP, usable 15 2 7 0xbfebfbff
CPU #1
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000f27 ebx = 00020809 ecx = 00000400 edx = bfebfbff
eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040
eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
Family: 15 Model: 2 Stepping: 7 Type: 0
CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM
Processor name string:
Feature flags:
Onboard FPU
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter
Model-Specific Registers
Physical Address Extensions
Machine Check Architecture
CMPXCHG8 instruction
Onboard APIC
SYSENTER/SYSEXIT
Memory Type Range Registers
Page Global Enable
Machine Check Architecture
CMOV instruction
Page Attribute Table
36-bit PSEs
CLFLUSH instruction
Debug Trace Store
ACPI via MSR
MMX support
FXSAVE and FXRESTORE instructions
SSE support
SSE2 support
CPU self snoop
Hyper-Threading
Automatic clock Control
Pending Break Enable
Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
Size: 8KB Sectored, 4-way associative.
line size=64 bytes.
No L3 cache
Instruction trace cache:
Size: 12K uOps 8-way associative.
L2 unified cache:
Size: 512KB Sectored, 8-way associative.
line size=64 bytes.
Number of reporting banks : 4
Number of extended MC registers : 12
Bank: 0 (0x400)
MC0CTL: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC0STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC0ADDR: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
Bank: 1 (0x404)
MC1CTL: 00000000 00000000 00000000 00000000
00000000 00000011 10000000 00000000
MC1STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC1ADDR: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
Bank: 2 (0x408)
MC2CTL: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 10000000
MC2STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC2ADDR: Couldn't read MSR 0x40a
Bank: 3 (0x40c)
MC3CTL: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 01111110
MC3STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC3ADDR: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
Number of logical processors supported within the physical package: 2
Connector type: Socket478 (PGA478 Socket)
Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf
http://developer.intel.com/design/pentium4/datashts/29864304.pdf
Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf
MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000006
MTRRphysMask0 (0x201): 0x0000000ff0000800
MTRRphysBase1 (0x202): 0x00000000e0000001
MTRRphysMask1 (0x203): 0x0000000ffc000800
MTRRphysBase2 (0x204): 0x0000000000000000
MTRRphysMask2 (0x205): 0x0000000000000000
MTRRphysBase3 (0x206): 0x0000000000000000
MTRRphysMask3 (0x207): 0x0000000000000000
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0505050505050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0505050505050505
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c00
2784.34 MHz processor (estimate).
CPU #2
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000f27 ebx = 01020809 ecx = 00000400 edx = bfebfbff
eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040
eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
Family: 15 Model: 2 Stepping: 7 Type: 0
CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM
Processor name string:
Feature flags:
Onboard FPU
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter
Model-Specific Registers
Physical Address Extensions
Machine Check Architecture
CMPXCHG8 instruction
Onboard APIC
SYSENTER/SYSEXIT
Memory Type Range Registers
Page Global Enable
Machine Check Architecture
CMOV instruction
Page Attribute Table
36-bit PSEs
CLFLUSH instruction
Debug Trace Store
ACPI via MSR
MMX support
FXSAVE and FXRESTORE instructions
SSE support
SSE2 support
CPU self snoop
Hyper-Threading
Automatic clock Control
Pending Break Enable
Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
Size: 8KB Sectored, 4-way associative.
line size=64 bytes.
No L3 cache
Instruction trace cache:
Size: 12K uOps 8-way associative.
L2 unified cache:
Size: 512KB Sectored, 8-way associative.
line size=64 bytes.
Number of reporting banks : 4
Number of extended MC registers : 12
Bank: 0 (0x400)
MC0CTL: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC0STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC0ADDR: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
Bank: 1 (0x404)
MC1CTL: 00000000 00000000 00000000 00000000
00000000 00000011 10000000 00000000
MC1STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC1ADDR: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
Bank: 2 (0x408)
MC2CTL: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 10000000
MC2STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC2ADDR: Couldn't read MSR 0x40a
Bank: 3 (0x40c)
MC3CTL: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 01111110
MC3STATUS: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
MC3ADDR: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
Number of logical processors supported within the physical package: 2
Connector type: Socket478 (PGA478 Socket)
Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf
http://developer.intel.com/design/pentium4/datashts/29864304.pdf
Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf
MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000006
MTRRphysMask0 (0x201): 0x0000000ff0000800
MTRRphysBase1 (0x202): 0x00000000e0000001
MTRRphysMask1 (0x203): 0x0000000ffc000800
MTRRphysBase2 (0x204): 0x0000000000000000
MTRRphysMask2 (0x205): 0x0000000000000000
MTRRphysBase3 (0x206): 0x0000000000000000
MTRRphysMask3 (0x207): 0x0000000000000000
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0505050505050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0505050505050505
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c00
2784.36 MHz processor (estimate).
|
