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2003-03-13ident P4 celeronsdavej1-2/+10
2003-03-07recognise D1 stepping P4sdavej1-1/+4
2003-02-11add 0x before versiondavej1-2/+2
2003-02-10Add various other info about certain CPUs which may get printeddavej1-1/+9
2003-01-18Decode cache sizes before CPU determination.davej4-9/+12
2003-01-18Some L2 cache sizes were marked as L3davej1-8/+8
2003-01-06compile fixes.davej1-3/+2
2002-12-30Celeron idents.davej1-14/+21
2002-12-13Dump microcode revisiondavej3-1/+43
2002-11-27Decode brand fielddavej2-6/+28
2002-11-27Add recognition for mobile pentium III and P3Mdavej1-30/+42
2002-11-19socket603davej1-5/+5
2002-11-19F27 isn't a Xeondavej1-2/+2
2002-11-12Change cacheinfo to use lookup tabledavej4-337/+223
2002-11-12P6 family MSR decodingdavej2-0/+43
2002-11-12Dump various P4 MSRsdavej3-1/+99
2002-11-11Some strings got too long for one line.davej1-3/+4
2002-11-11debug infodavej1-1/+8
2002-11-02* identify.c: Print out URLs to errata/datasheet if known.davej1-1/+26
2002-10-30feature flag handling cleanupdavej1-3/+2
2002-10-22Northwood is a xeondavej1-2/+2
2002-09-24more ppro steppingsdavej1-3/+24
2002-07-24add more P4 codenamesdavej1-3/+3
2002-07-14reformat binary outputdavej1-3/+1
2002-07-12identify C1 stepping of P4 Xeondavej1-1/+4
2002-07-12large clean up of intel code using tuple macrodavej1-288/+275
2002-06-08Add four more cache descriptors.davej1-2/+14
2002-06-06* Intel/bluesmoke.c: Intel doesn't have the MISC register.davej1-4/+1
2002-06-06* Intel/identify.c: Add socket types for each CPU.davej1-1/+21
2002-05-24Recognise C0 stepping of P4 Xeondavej1-1/+4
2002-05-232002-04-23 Dave Jones <davej@suse.de>davej1-8/+7
2002-05-142002-05-15 Randy Dunlap <randy.dunlap@verizon.net>davej3-16/+33
2002-05-02add a todo for later.davej1-1/+2
2002-04-26 * Intel/identify.c: Recognise another P4 stepping. (E0)davej1-1/+4
2002-04-17* Intel/identify.c: Add another stepping.davej1-2/+2
2002-03-142002-03-10 Sami Farin <safari@iki.fi>davej1-14/+64
2001-12-12Make celeron coppermines show chip core revision too.davej1-4/+5
2001-12-11oops, missed some \n'sdavej1-4/+4
2001-12-11Recognise more copperminesdavej1-3/+3
2001-12-11Recognise some extra Intel CPUsdavej1-5/+8
2001-12-10More white space fix.davej1-2/+2
2001-12-10Cluster register dumps together.davej1-1/+4
2001-12-10Rewrite flag handling.davej1-2/+2
2001-12-10Make Intel cachesize output look 99.9% the same as the AMD output.davej1-23/+23
2001-12-10Now identifies Celerons from Pentiums using cache size.davej3-7/+30
2001-12-10Intel cache descriptor parser. Borrowed from the linux kernel.davej1-0/+110
2001-12-10use get_model_name() instead of duplicating same code in everydavej1-1/+6
2001-12-10Intel/eblcr.c: added 'const' to buscode[][] and mult[][] in orderdavej1-2/+2
2001-12-10Clean up externsdavej3-10/+53
2001-12-10Don't try to read eblcr if we don't ask for it.davej1-5/+8
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