diff options
| author | Dave Jones <davej@redhat.com> | 2011-03-08 18:49:30 -0500 |
|---|---|---|
| committer | Dave Jones <davej@redhat.com> | 2011-03-08 18:49:30 -0500 |
| commit | dc7d82f87a1fb020ca212a450a8988ffeeb0e85d (patch) | |
| tree | 705d5bee8c44bc33f94468ee95b1d03caeb37b49 | |
| parent | edee29af8e388f21ec1f2265186d561418b4ddf2 (diff) | |
Start decoding IDA
| -rw-r--r-- | Intel/Intel.h | 4 | ||||
| -rw-r--r-- | Intel/MSR-IDA.c | 42 | ||||
| -rw-r--r-- | Intel/info.c | 10 | ||||
| -rw-r--r-- | Makefile | 1 |
4 files changed, 53 insertions, 4 deletions
diff --git a/Intel/Intel.h b/Intel/Intel.h index bb6d71b..838e6a4 100644 --- a/Intel/Intel.h +++ b/Intel/Intel.h @@ -3,11 +3,15 @@ extern void decode_Intel_caches (struct cpudata *cpu, int output); extern void show_Intel_caches(struct cpudata *cpu); extern void decode_Intel_machine_check(int cpunum, int family); + extern void dump_p4_MSRs(struct cpudata *cpu); extern void dump_p6_MSRs(struct cpudata *cpu); extern void dump_performance_MSRs(struct cpudata *cpu); extern void dump_thermal_MSRs(struct cpudata *cpu); +extern void dump_IDA_MSRs(struct cpudata *cpu); + extern void decode_microcode(struct cpudata *cpu); + extern void Identify_Intel_family6pentium(struct cpudata *cpu); extern void Identify_Intel_family6core(struct cpudata *cpu); extern void Identify_Intel_family15(struct cpudata *cpu); diff --git a/Intel/MSR-IDA.c b/Intel/MSR-IDA.c new file mode 100644 index 0000000..235f992 --- /dev/null +++ b/Intel/MSR-IDA.c @@ -0,0 +1,42 @@ +/* + * (C) 2011 Dave Jones. + * + * Licensed under the terms of the GNU GPL License version 2. + * + */ + +#include <stdio.h> +#include <unistd.h> +#include <sys/types.h> +#include "../x86info.h" +#include "Intel.h" + +void dump_IDA_MSRs(struct cpudata *cpu) +{ + unsigned long long val = 0; + unsigned int eax, ebx, ecx, edx; + + if (!user_is_root) + return; + + if (cpu->cpuid_level < 6) + return; + + cpuid_count(cpu->number, 6, 0, &eax, &ebx, &ecx, &edx); + printf("Dynamic Acceleration MSRs:\n"); + printf(" Opportunistic performance operation "); + if ((eax & (1 << 1)) == 1) + printf("enabled by BIOS\n"); + else + printf("disabled by BIOS (or not supported)\n"); + + if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) != 1) + return; + + if ((val & (1L << 38)) == 1) { + printf(" IA32_MISC_ENABLES[38] is 1 (disabled opportunistic performance operation)\n"); + return; + } + + printf("\n"); +} diff --git a/Intel/info.c b/Intel/info.c index dae362d..2be9062 100644 --- a/Intel/info.c +++ b/Intel/info.c @@ -120,10 +120,12 @@ void display_extended_Intel_info(struct cpudata *cpu) if (show_msr) { if (cpu->family == 0xf) dump_p4_MSRs(cpu); - if (cpu->family == 0x6 && (cpu->model == 9 || model(cpu) >= 13)) { - dump_performance_MSRs(cpu); - dump_thermal_MSRs(cpu); - } + + dump_performance_MSRs(cpu); + + dump_thermal_MSRs(cpu); + + dump_IDA_MSRs(cpu); } if (show_eblcr) { @@ -62,6 +62,7 @@ X86INFO_SRC =\ Intel/MSR-P6.c\ Intel/MSR-performance.c\ Intel/MSR-thermal.c\ + Intel/MSR-IDA.c\ Intel/microcode.c\ Intel/topology.c\ \ |