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authorDave Jones <davej@redhat.com>2011-02-18 14:24:23 -0500
committerDave Jones <davej@redhat.com>2011-02-18 14:24:23 -0500
commit16809ddb1f5577608289a6c35a7bc8064cebfd06 (patch)
treebb11043945dafec3f7dad2981fc4f998f6f48709
parentd28aa3142537a2a22814f52111c3cd4afa2a27bc (diff)
Split MSR-PM into thermal and performance
-rw-r--r--Intel/Intel.h3
-rw-r--r--Intel/MSR-performance.c44
-rw-r--r--Intel/MSR-thermal.c (renamed from Intel/MSR-PM.c)39
-rw-r--r--Intel/info.c6
-rw-r--r--Makefile3
5 files changed, 60 insertions, 35 deletions
diff --git a/Intel/Intel.h b/Intel/Intel.h
index 9d49aa5..a31078a 100644
--- a/Intel/Intel.h
+++ b/Intel/Intel.h
@@ -5,7 +5,8 @@ extern void show_Intel_caches(struct cpudata *cpu);
extern void decode_Intel_bluesmoke(int cpunum, int family);
extern void dump_p4_MSRs(struct cpudata *cpu);
extern void dump_p6_MSRs(struct cpudata *cpu);
-extern void dump_centrino_MSRs(struct cpudata *cpu);
+extern void dump_performance_MSRs(struct cpudata *cpu);
+extern void dump_thermal_MSRs(struct cpudata *cpu);
extern void decode_microcode(struct cpudata *cpu);
extern void Identify_Intel_family6pentium(struct cpudata *cpu);
extern void Identify_Intel_family6core(struct cpudata *cpu);
diff --git a/Intel/MSR-performance.c b/Intel/MSR-performance.c
new file mode 100644
index 0000000..4bf2081
--- /dev/null
+++ b/Intel/MSR-performance.c
@@ -0,0 +1,44 @@
+/*
+ * (C) 2011 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "../x86info.h"
+#include "Intel.h"
+
+void dump_performance_MSRs(struct cpudata *cpu)
+{
+ unsigned long long val = 0;
+
+ if (!user_is_root)
+ return;
+
+ printf("Performance MSRs:\n");
+ if (read_msr(cpu->number, MSR_IA32_PERF_STATUS, &val) == 1)
+ printf(" MSR_IA32_PERF_STATUS: 0x%llx\n", val);
+
+ if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) == 1) {
+ printf(" MSR_IA32_MISC_ENABLE: 0x%llx", val);
+ printf(" [Enabled: ");
+ if (val & (1<<3))
+ printf("TCC ");
+ if (val & (1<<7))
+ printf("PerfMon ");
+ if (val & (1<<10))
+ printf("FERR# ");
+ if (val & (1<<11))
+ printf("noBTS ");
+ if (val & (1<<12))
+ printf("noPEBS ");
+ if (val & (1<<16))
+ printf("EnhancedSpeedStep ");
+
+ printf("]\n");
+ }
+ printf("\n");
+}
diff --git a/Intel/MSR-PM.c b/Intel/MSR-thermal.c
index d5245ab..157fdb1 100644
--- a/Intel/MSR-PM.c
+++ b/Intel/MSR-thermal.c
@@ -1,10 +1,8 @@
/*
- * (C) 2002 Dave Jones.
+ * (C) 2011 Dave Jones.
*
* Licensed under the terms of the GNU GPL License version 2.
*
- * Intel Pentium M specific MSR information
- * See 24547203.pdf for more details.
*/
#include <stdio.h>
@@ -13,43 +11,22 @@
#include "../x86info.h"
#include "Intel.h"
-void dump_centrino_MSRs(struct cpudata *cpu)
+void dump_thermal_MSRs(struct cpudata *cpu)
{
unsigned long long val = 0;
- int tcc = 0;
if (!user_is_root)
return;
- printf("Performance MSRs:\n");
- if (read_msr(cpu->number, MSR_IA32_PERF_STATUS, &val) == 1)
- printf(" MSR_IA32_PERF_STATUS: 0x%llx\n", val);
-
- if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) == 1) {
- printf(" MSR_IA32_MISC_ENABLE: 0x%llx", val);
- printf(" [Enabled: ");
- if (val & (1<<3)) {
- printf("TCC ");
- tcc = 1;
- }
- if (val & (1<<7))
- printf("PerfMon ");
- if (val & (1<<10))
- printf("FERR# ");
- if (val & (1<<11))
- printf("noBTS ");
- if (val & (1<<12))
- printf("noPEBS ");
- if (val & (1<<16))
- printf("EnhancedSpeedStep ");
-
- printf("]\n");
- }
- printf("\n");
+ if (read_msr(cpu->number, MSR_IA32_MISC_ENABLE, &val) != 1)
+ return;
+ // tcc enabled ?
+ if (!(val & (1<<3)))
+ return;
printf("Thermal MSRs:\n");
- if (tcc && read_msr(cpu->number, MSR_PM_THERM2_CTL, &val) == 1) { /* THERM2_CTL */
+ if (read_msr(cpu->number, MSR_PM_THERM2_CTL, &val) == 1) { /* THERM2_CTL */
printf(" MSR_PM_THERM2_CTL: 0x%llx [Thermal monitor: %d]\n",
val, (val & (1<<16)) ? 2 : 1);
}
diff --git a/Intel/info.c b/Intel/info.c
index 166ccbf..20a3afa 100644
--- a/Intel/info.c
+++ b/Intel/info.c
@@ -116,8 +116,10 @@ void display_Intel_info(struct cpudata *cpu)
if (show_msr) {
if (cpu->family == 0xf)
dump_p4_MSRs(cpu);
- if (cpu->family == 0x6 && (cpu->model == 9 || model(cpu) >= 13))
- dump_centrino_MSRs(cpu);
+ if (cpu->family == 0x6 && (cpu->model == 9 || model(cpu) >= 13)) {
+ dump_performance_MSRs(cpu);
+ dump_thermal_MSRs(cpu);
+ }
}
if (show_eblcr) {
diff --git a/Makefile b/Makefile
index 95381e0..4a3d1df 100644
--- a/Makefile
+++ b/Makefile
@@ -60,7 +60,8 @@ X86INFO_SRC =\
Intel/eblcr.c\
Intel/MSR-P4.c\
Intel/MSR-P6.c\
- Intel/MSR-PM.c\
+ Intel/MSR-performance.c\
+ Intel/MSR-thermal.c\
Intel/microcode.c\
Intel/topology.c\
\