summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorEric Anholt <eric@anholt.net>2017-09-28 11:41:31 -0700
committerEric Anholt <eric@anholt.net>2017-10-10 11:42:05 -0700
commit7f3b8906979ba5f2c1876b4eb2c0b85314107511 (patch)
tree21aa1b23d63d1ff5f96600559a803ec4a6f47650
parentbe11251e3c0f4ef2ad57aa83dbb480bc2b95328a (diff)
broadcom/vc5: Fix depth and stencil clear values.
I had misread the packet description: We always have a 32f depth, and a separate u8 stencil.
-rw-r--r--src/broadcom/cle/v3d_packet_v33.xml2
-rw-r--r--src/gallium/drivers/vc5/vc5_context.h3
-rw-r--r--src/gallium/drivers/vc5/vc5_draw.c18
-rw-r--r--src/gallium/drivers/vc5/vc5_rcl.c3
4 files changed, 11 insertions, 15 deletions
diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 82709c3cd6..bbfe0a991d 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -557,7 +557,7 @@
<packet code="121" name="Tile Rendering Mode Configuration (Z Stencil Clear Values)" cl="R">
<field name="unused" size="16" start="48" type="uint"/>
- <field name="Z/S Clear Value" size="32" start="16" type="uint"/>
+ <field name="Z Clear Value" size="32" start="16" type="float"/>
<field name="Stencil/VG Mask Clear Value" size="8" start="8" type="uint"/>
<field name="sub-id" size="4" start="0" type="uint" default="3"/>
diff --git a/src/gallium/drivers/vc5/vc5_context.h b/src/gallium/drivers/vc5/vc5_context.h
index cac623adf2..472f039859 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -245,7 +245,8 @@ struct vc5_job {
*/
uint32_t resolve;
uint32_t clear_color[2];
- uint32_t clear_zs; /**< 24-bit unorm depth/stencil */
+ float clear_z;
+ uint8_t clear_s;
/**
* Set if some drawing (triangles, blits, or just a glClear()) has
diff --git a/src/gallium/drivers/vc5/vc5_draw.c b/src/gallium/drivers/vc5/vc5_draw.c
index 555e822a71..b7f8a7819f 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -561,21 +561,15 @@ vc5_clear(struct pipe_context *pctx, unsigned buffers,
rsc->initialized_buffers |= (buffers & PIPE_CLEAR_COLOR0);
}
- if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
+ unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
+ if (zsclear) {
struct vc5_resource *rsc =
vc5_resource(vc5->framebuffer.zsbuf->texture);
- unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
- if (buffers & PIPE_CLEAR_DEPTH) {
- job->clear_zs |=
- util_pack_z_stencil(PIPE_FORMAT_S8_UINT_Z24_UNORM,
- depth, 0);
- }
- if (buffers & PIPE_CLEAR_STENCIL) {
- job->clear_zs |=
- util_pack_z_stencil(PIPE_FORMAT_S8_UINT_Z24_UNORM,
- 0, stencil);
- }
+ if (zsclear & PIPE_CLEAR_DEPTH)
+ job->clear_z = depth;
+ if (zsclear & PIPE_CLEAR_STENCIL)
+ job->clear_s = stencil;
rsc->initialized_buffers |= zsclear;
}
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c b/src/gallium/drivers/vc5/vc5_rcl.c
index e55a29772e..ebc77dcce0 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -182,7 +182,8 @@ vc5_emit_rcl(struct vc5_job *job)
/* Ends rendering mode config. */
cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
clear) {
- clear.z_s_clear_value = job->clear_zs;
+ clear.z_clear_value = job->clear_z;
+ clear.stencil_vg_mask_clear_value = job->clear_s;
};
/* Always set initial block size before the first branch, which needs