~ramaling/linux - Ram's kernel repositories

Age	Commit message (Expand)	Author	Files	Lines
2017-08-23	Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/...	Stephen Boyd	12	-84/+560
2017-08-17	clk: renesas: r8a7796: Add USB3.0 clock	Hiromitsu Yamasaki	1	-0/+1
2017-08-17	clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY	Yoshihiro Shimoda	3	-0/+194
2017-08-16	clk: renesas: cpg-mssr: Add R8A77995 support	Geert Uytterhoeven	5	-0/+249
2017-08-16	clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks	Geert Uytterhoeven	2	-1/+26
2017-08-16	clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3	Geert Uytterhoeven	4	-37/+41
2017-07-21	clk: Convert to using %pOF instead of full_name	Rob Herring	2	-3/+2
2017-07-19	clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table	Wolfram Sang	1	-26/+20
2017-07-19	clk: renesas: rcar-gen3-cpg: Drop superfluous variable	Wolfram Sang	1	-2/+1
2017-07-17	clk: renesas: Allow compile-testing of all (sub)drivers	Geert Uytterhoeven	1	-19/+19
2017-07-17	clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks	Geert Uytterhoeven	1	-0/+7
2017-07-17	clk: renesas: div6: Document fields used for parent selection	Geert Uytterhoeven	1	-0/+3
2017-06-19	clk: renesas: cpg-mssr: Use of_device_get_match_data() helper	Geert Uytterhoeven	1	-1/+1
2017-05-24	clk: renesas: r8a7794: Add new CPG/MSSR driver	Geert Uytterhoeven	5	-2/+266
2017-05-24	clk: renesas: r8a7792: Add new CPG/MSSR driver	Geert Uytterhoeven	5	-2/+232
2017-05-24	clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driver	Geert Uytterhoeven	5	-2/+302
2017-05-24	clk: renesas: r8a7790: Add new CPG/MSSR driver	Geert Uytterhoeven	5	-1/+298
2017-05-24	clk: renesas: Rework Kconfig and Makefile logic	Geert Uytterhoeven	3	-36/+134
2017-05-24	clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()	Geert Uytterhoeven	1	-1/+1
2017-05-15	clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0	Geert Uytterhoeven	1	-13/+26
2017-05-15	clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct access	Geert Uytterhoeven	2	-2/+2
2017-05-15	clk: renesas: Do not build clk-div6 for R8A7792	Geert Uytterhoeven	1	-1/+1
2017-05-15	clk: renesas: r8a7796: Add INTC-EX clock	Takeshi Kihara	1	-0/+1
2017-05-15	clk: renesas: r8a7796: Add PCIe clocks	Harunobu Kurokawa	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add PWM clock	Ryo Kodama	1	-0/+1
2017-05-15	clk: renesas: r8a7796: Add HS-USB clock	Kazuya Mizuguchi	1	-0/+1
2017-05-15	clk: renesas: r8a7796: Add Sound DVC clocks	Kazuya Mizuguchi	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add Sound SRC clock	Kazuya Mizuguchi	1	-0/+13
2017-05-15	clk: renesas: r8a7796: Add Sound SSI clock	Kazuya Mizuguchi	1	-0/+11
2017-05-15	clk: renesas: r8a7796: Add USB-DMAC clocks	Hiromitsu Yamasaki	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add Audio-DMAC clocks	Hiromitsu Yamasaki	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add EHCI/OHCI clocks	Kazuya Mizuguchi	1	-0/+2
2017-05-15	clk: renesas: r8a7796: Add HDMI clock	Koji Matsuoka	1	-0/+2
2017-05-15	clk: renesas: r8a7795: Add HS-USB ch3 clock	Takeshi Kihara	1	-0/+1
2017-05-15	clk: renesas: r8a7795: Add USB-DMAC ch3 clock	Takeshi Kihara	1	-0/+2
2017-05-15	clk: renesas: r8a7795: Add EHCI/OHCI ch3 clock	Takeshi Kihara	1	-0/+1
2017-05-15	clk: renesas: r8a7745: Remove PLL configs for MD19=0	Geert Uytterhoeven	1	-11/+2
2017-05-15	clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks	Geert Uytterhoeven	1	-4/+0
2017-05-15	clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2	Geert Uytterhoeven	1	-4/+19
2017-03-30	clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0	Geert Uytterhoeven	1	-11/+27
2017-03-30	clk: renesas: r8a7795: Add support for R-Car H3 ES2.0	Geert Uytterhoeven	1	-50/+151
2017-03-30	clk: renesas: cpg-mssr: Add support for fixing up clock tables	Geert Uytterhoeven	2	-0/+72
2017-03-21	clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0	Geert Uytterhoeven	1	-0/+24
2017-03-21	clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()	Geert Uytterhoeven	4	-4/+6
2017-03-21	clk: renesas: r8a7796: Reformat core clock table	Geert Uytterhoeven	1	-6/+6
2017-03-21	clk: renesas: r8a7795: Reformat core clock table	Geert Uytterhoeven	1	-10/+10
2017-03-21	clk: renesas: r8a7796: Correct name of watchdog clock	Geert Uytterhoeven	1	-1/+1
2017-03-21	clk: renesas: r8a7795: Correct name of watchdog clock	Geert Uytterhoeven	1	-1/+1
2017-03-21	clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs	Geert Uytterhoeven	1	-2/+2
2017-03-06	clk: renesas: r8a7796: Add IMR clocks	Sergei Shtylyov	1	-0/+2