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:
~ramaling/linux
dg2_enabling_ww4.2
dg2_enabling_ww49.3
dg2_enabling_ww5.5
dg2_enabling_ww50.3
dg2_enabling_ww50.4
dg2_enabling_ww51.3
dg2_enabling_ww6.2
dg2_enabling_ww7.5
dg2_enabling_ww8.3
dg2_for_ci_ww8.5
drm-tip
drm_tip_ww49.2
flat-ccs-v4
flat-ccs-v5
flat-ccs-v6
flat-ccs-v7
flat-ccs-v8
flat-ccs-ww10.07
flat-ccs-ww10.2
flat-ccs-ww10.3
flat-ccs-ww10.5
flat-ccs-ww11.01
flat-ccs-ww12.02
flat-ccs-ww9.4
flat-ccs-ww9.4-wip
flat-ccs-ww9.7
igt_vm_bind_upstream_7
master
vm_bind_upstream_7
vm_bind_v2
vm_bind_v2_2
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path:
root
/
drivers
/
clk
/
pistachio
Age
Commit message (
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)
Author
Files
Lines
2021-08-12
clk: pistachio: Make it selectable for generic MIPS kernel
Jiaxun Yang
1
-0
/
+8
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422
Thomas Gleixner
4
-16
/
+4
2019-05-21
treewide: Add SPDX license identifier - Makefile/Kconfig
Thomas Gleixner
1
-0
/
+1
2018-11-06
clk: pistachio: constify clk_ops structures
Julia Lawall
1
-4
/
+4
2015-08-26
clk: pistachio: correct critical clock list
Damien.Horsley
1
-5
/
+14
2015-08-26
clk: pistachio: Fix PLL rate calculation in integer mode
Zdenko Pulitika
1
-2
/
+46
2015-08-26
clk: pistachio: Fix override of clk-pll settings from boot loader
Zdenko Pulitika
1
-3
/
+2
2015-08-26
clk: pistachio: Fix 32bit integer overflows
Zdenko Pulitika
2
-21
/
+19
2015-08-24
clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
Stephen Boyd
1
-2
/
+2
2015-07-20
clk: pistachio: Include clk.h
Stephen Boyd
1
-0
/
+1
2015-06-04
clk: pistachio: Add sanity checks on PLL configuration
Kevin Cernekee
1
-4
/
+79
2015-06-04
clk: pistachio: Lock the PLL when enabled upon rate change
Ezequiel Garcia
1
-18
/
+10
2015-06-04
clk: pistachio: Add a pll_lock() helper for clarity
Ezequiel Garcia
1
-4
/
+8
2015-03-31
CLK: Pistachio: Register external clock gates
Andrew Bresticker
1
-0
/
+21
2015-03-31
CLK: Pistachio: Register system interface gate clocks
Andrew Bresticker
1
-0
/
+42
2015-03-31
CLK: Pistachio: Register peripheral clocks
Andrew Bresticker
1
-0
/
+67
2015-03-31
CLK: Pistachio: Register core clocks
Andrew Bresticker
2
-0
/
+200
2015-03-31
CLK: Pistachio: Add PLL driver
Andrew Bresticker
3
-0
/
+452
2015-03-31
CLK: Add basic infrastructure for Pistachio clocks
Andrew Bresticker
3
-0
/
+265