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authorSebastian Andrzej Siewior <bigeasy@linutronix.de>2012-10-30 19:52:24 +0100
committerFelipe Balbi <balbi@ti.com>2012-10-31 15:21:01 +0200
commit515ba29cd7b571da45365e4db80c1b6905869ef3 (patch)
tree2351e46c28558ac37fc2258925db8da736195286 /drivers/usb/musb/musb_gadget_ep0.c
parentb11e94d03726c5dbee0d9a841a025313504e90f4 (diff)
usb: musb: avoid FADDR read access
This is part of the workaround for AM35x advisory Advisory 1.1.20. The advisory says that the IPSS bridge can't handle 8 & 16 bit read access. An 8bit read access to FADDR results in an 32bit read access which also reads INTRTX and therefore may lose interrupts. This patch removes any reads to FADDR as they are not really required. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/musb/musb_gadget_ep0.c')
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index e40d7647caf1..c9c1ac4e075f 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -673,10 +673,8 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
csr = musb_readw(regs, MUSB_CSR0);
len = musb_readb(regs, MUSB_COUNT0);
- dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
- csr, len,
- musb_readb(mbase, MUSB_FADDR),
- decode_ep0stage(musb->ep0_state));
+ dev_dbg(musb->controller, "csr %04x, count %d, ep0stage %s\n",
+ csr, len, decode_ep0stage(musb->ep0_state));
if (csr & MUSB_CSR0_P_DATAEND) {
/*