diff options
author | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-28 12:26:19 -0800 |
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committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-29 12:28:11 -0800 |
commit | 7182414e25304d0f8c7071756b6e986227c70872 (patch) | |
tree | acfd2e98a78d52797109705686549f8c63aa42c0 /drivers/extcon | |
parent | 91ba2c8be4b7eef3c9c424ddd862cdb302f252f3 (diff) |
drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v7:
* Remove unnecessary comments, leftovers (Ville)
* No need for explicit val &= ~ (Ville)
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
[manasi: fixup the line longer than 100 chars while applying]
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-8-manasi.d.navare@intel.com
Diffstat (limited to 'drivers/extcon')
0 files changed, 0 insertions, 0 deletions