diff options
| author | Gerhard Sittig <gsi@denx.de> | 2013-07-22 14:14:40 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-27 17:50:38 -0700 |
| commit | aa514ce34b65e3dc01f95a0b470b39bbb7e09998 (patch) | |
| tree | 6d83d3f8e7560e5cd46fafe39960cd78cdfdc815 /drivers/clk/clk-gate.c | |
| parent | 29f79cb713c5173457b80602adab357403f22c48 (diff) | |
clk: wrap I/O access for improved portability
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-gate.c')
| -rw-r--r-- | drivers/clk/clk-gate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 2b28a004c19e..4a58c55255bd 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (set) reg |= BIT(gate->bit_idx); } else { - reg = readl(gate->reg); + reg = clk_readl(gate->reg); if (set) reg |= BIT(gate->bit_idx); @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) reg &= ~BIT(gate->bit_idx); } - writel(reg, gate->reg); + clk_writel(reg, gate->reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); @@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw) u32 reg; struct clk_gate *gate = to_clk_gate(hw); - reg = readl(gate->reg); + reg = clk_readl(gate->reg); /* if a set bit disables this clk, flip it before masking */ if (gate->flags & CLK_GATE_SET_TO_DISABLE) |