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authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>2014-09-05 12:23:49 +0200
committerSimon Horman <horms+renesas@verge.net.au>2014-09-09 11:29:27 +0900
commita742795be9ceae2853ca71f216193f29da151da8 (patch)
tree4efd7cc0ec33e44aea5c5b1c3399c8780bfe29f0 /arch
parent0dce5454d5c258582a7da5590332d9e085886bf7 (diff)
ARM: shmobile: Initial Alt board device tree
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> [uli: reduced to minimum, added cmt, enabled scif2, split off from SoC] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts47
2 files changed, 49 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3ddeb9..81c1df94f2f3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -375,7 +375,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7790-lager.dtb \
- r8a7779-marzen.dtb
+ r8a7779-marzen.dtb \
+ r8a7794-alt.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
new file mode 100644
index 000000000000..79d06ef017a0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -0,0 +1,47 @@
+/*
+ * Device Tree Source for the Alt board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+
+/ {
+ model = "Alt";
+ compatible = "renesas,alt", "renesas,r8a7794";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&cmt0 {
+ status = "ok";
+};
+
+&scif2 {
+ status = "ok";
+};