diff options
| author | Michael Ellerman <mpe@ellerman.id.au> | 2017-04-20 15:35:09 +1000 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2017-04-21 20:30:51 +0800 |
| commit | 0f89f6e188fa929b6de49c00c73f5731a6bd6bac (patch) | |
| tree | 10a4965ef59f1878b873f8ddbbdf017a64b72dc7 /arch/powerpc/crypto | |
| parent | a9943a0ad19f4a23bb5c4217df0fb37feb7ac339 (diff) | |
crypto: crct10dif-vpmsum - Fix missing preempt_disable()
In crct10dif_vpmsum() we call enable_kernel_altivec() without first
disabling preemption, which is not allowed.
It used to be sufficient just to call pagefault_disable(), because that
also disabled preemption. But the two were decoupled in commit 8222dbe21e79
("sched/preempt, mm/fault: Decouple preemption from the page fault
logic") in mid 2015.
The crct10dif-vpmsum code inherited this bug from the crc32c-vpmsum code
on which it was modelled.
So add the missing preempt_disable/enable(). We should also call
disable_kernel_fp(), although it does nothing by default, there is a
debug switch to make it active and all enables should be paired with
disables.
Fixes: b01df1c16c9a ("crypto: powerpc - Add CRC-T10DIF acceleration")
Acked-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'arch/powerpc/crypto')
| -rw-r--r-- | arch/powerpc/crypto/crct10dif-vpmsum_glue.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/crypto/crct10dif-vpmsum_glue.c b/arch/powerpc/crypto/crct10dif-vpmsum_glue.c index bebfc329f746..02ea277863d1 100644 --- a/arch/powerpc/crypto/crct10dif-vpmsum_glue.c +++ b/arch/powerpc/crypto/crct10dif-vpmsum_glue.c @@ -44,10 +44,13 @@ static u16 crct10dif_vpmsum(u16 crci, unsigned char const *p, size_t len) if (len & ~VMX_ALIGN_MASK) { crc <<= 16; + preempt_disable(); pagefault_disable(); enable_kernel_altivec(); crc = __crct10dif_vpmsum(crc, p, len & ~VMX_ALIGN_MASK); + disable_kernel_altivec(); pagefault_enable(); + preempt_enable(); crc >>= 16; } |