diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2012-12-19 10:18:42 -0800 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-01-28 13:27:28 +0100 |
| commit | 87e4ee759f44f8d1e0f039bc9ba2ef57ea2a9bee (patch) | |
| tree | d88d48b9d59acb7aabd6b382a2a53874c5b649f8 /arch/arm/mach-zynq | |
| parent | 03377e5852309edc90acbb03f6e2dfef70c020f2 (diff) | |
arm: zynq: timer: Set clock_event cpumask
The timers are common to both A9 cores, so let's set the clock
event struct's cpumask accordingly, to all possible CPUs.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Diffstat (limited to 'arch/arm/mach-zynq')
| -rw-r--r-- | arch/arm/mach-zynq/timer.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 7b2e04776a54..f9fbc9c1e7a6 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -267,6 +267,7 @@ static void __init zynq_ttc_setup_clockevent(struct device_node *np, ttcce->ce.set_mode = xttcps_set_mode; ttcce->ce.rating = 200; ttcce->ce.irq = irq; + ttcce->ce.cpumask = cpu_possible_mask; __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |