tools/null_state_gen: Add GEN9 golden context batch buffer creation

Modifications to 'null_state_gen' so it can generate GEN9
golden context batch buffer source for SKL.

v2: - rebased on top of gen8 changes (Mika)
    - fixed state base address command size (Mika)
    - base address size macro as pages (Mika)

v3: - rebased on top of current master (Mika)
    - removed obsolete #includes (Mika)
    - added copyright (Mika)
    - render and component packing added (Mika)

Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Armin Reese <armin.c.reese@intel.com>
Cc: Volkin, Bradley D <bradley.d.volkin@intel.com>
Reviewed-by: Volkin, Bradley D <bradley.d.volkin@intel.com> (v2)
Signed-off-by: Armin Reese <armin.c.reese@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

3 files changed, 485 insertions, 3 deletions

diff --git a/tools/null_state_gen/Makefile.am b/tools/null_state_gen/Makefile.am
index 58fbd538..b131e0d3 100644
--- a/tools/null_state_gen/Makefile.am
+++ b/tools/null_state_gen/Makefile.am
@@ -8,9 +8,10 @@ intel_null_state_gen_SOURCES = 	\
 	intel_renderstate_gen6.c \
 	intel_renderstate_gen7.c \
 	intel_renderstate_gen8.c \
+	intel_renderstate_gen9.c \
 	intel_null_state_gen.c
 
-gens := 6 7 8
+gens := 6 7 8 9
 
 h = /tmp/intel_renderstate_gen$$gen.c
 state_headers: intel_null_state_gen
diff --git a/tools/null_state_gen/intel_null_state_gen.c b/tools/null_state_gen/intel_null_state_gen.c
index 353556ab..8024ac3d 100644
--- a/tools/null_state_gen/intel_null_state_gen.c
+++ b/tools/null_state_gen/intel_null_state_gen.c
@@ -35,14 +35,15 @@
 extern int gen6_setup_null_render_state(struct intel_batchbuffer *batch);
 extern int gen7_setup_null_render_state(struct intel_batchbuffer *batch);
 extern int gen8_setup_null_render_state(struct intel_batchbuffer *batch);
+extern int gen9_setup_null_render_state(struct intel_batchbuffer *batch);
 
 static int debug = 0;
 
 static void print_usage(char *s)
 {
 	fprintf(stderr, "%s: <gen>\n"
-		"     gen:     gen to generate for (6,7,8)\n",
-	       s);
+		"     gen:     gen to generate for (6,7,8,9)\n",
+		s);
 }
 
 /* Creates the intel_renderstate_genX.c file for the particular
@@ -132,6 +133,9 @@ static int do_generate(int gen)
 	case 8:
 		null_state_gen = gen8_setup_null_render_state;
 		break;
+	case 9:
+		null_state_gen = gen9_setup_null_render_state;
+		break;
 	}
 
 	if (null_state_gen == NULL) {
diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c
new file mode 100644
index 00000000..6f808f81
--- /dev/null
+++ b/tools/null_state_gen/intel_renderstate_gen9.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *	Armin Reese <armin.c.reese@intel.com>
+ *	Mika Kuoppala <mika.kuoppala@intel.com>
+ */
+
+#include "intel_batchbuffer.h"
+#include <lib/gen9_render.h>
+#include <lib/intel_reg.h>
+
+static void gen8_emit_wm(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2));
+	OUT_BATCH(GEN7_WM_LEGACY_DIAMOND_LINE_RASTERIZATION);
+}
+
+static void gen8_emit_ps(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0); /* kernel hi */
+	OUT_BATCH(GEN7_PS_SPF_MODE);
+	OUT_BATCH(0); /* scratch space stuff */
+	OUT_BATCH(0); /* scratch hi */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0); // kernel 1
+	OUT_BATCH(0); /* kernel 1 hi */
+	OUT_BATCH(0); // kernel 2
+	OUT_BATCH(0); /* kernel 2 hi */
+}
+
+static void gen8_emit_sf(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(1 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT |
+		  1 << GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT |
+		  GEN7_SF_POINT_WIDTH_FROM_SOURCE |
+		  8);
+}
+
+static void gen8_emit_vs(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN6_3DSTATE_VS | (9 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(GEN7_VS_FLOATING_POINT_MODE_ALTERNATE);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void gen8_emit_hs(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN7_3DSTATE_HS | (9 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT);
+	OUT_BATCH(0);
+}
+
+static void gen8_emit_raster(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0.0);
+	OUT_BATCH(0.0);
+	OUT_BATCH(0.0);
+}
+
+static void gen8_emit_urb(struct intel_batchbuffer *batch)
+{
+	const int vs_entries = 64;
+	const int vs_size = 2;
+	const int vs_start = 4;
+
+	OUT_BATCH(GEN7_3DSTATE_URB_VS);
+	OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
+
+	OUT_BATCH(GEN7_3DSTATE_URB_HS);
+	OUT_BATCH(0x0f << 25);
+
+	OUT_BATCH(GEN7_3DSTATE_URB_DS);
+	OUT_BATCH(0x0f << 25);
+
+	OUT_BATCH(GEN7_3DSTATE_URB_GS);
+	OUT_BATCH(0x0f << 25);
+}
+
+static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY);
+	OUT_BATCH(_3DPRIM_TRILIST);
+}
+
+static void gen8_emit_so_decl_list(struct intel_batchbuffer *batch)
+{
+	const int num_decls = 128;
+	int i;
+
+	OUT_BATCH(GEN8_3DSTATE_SO_DECL_LIST |
+		(((2 * num_decls) + 3) - 2) /* DWORD count - 2 */);
+	OUT_BATCH(0);
+	OUT_BATCH(num_decls);
+
+	for (i = 0; i < num_decls; i++) {
+		OUT_BATCH(0);
+		OUT_BATCH(0);
+	}
+}
+
+static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index)
+{
+	OUT_BATCH(GEN8_3DSTATE_SO_BUFFER | (8 - 2));
+	OUT_BATCH(index << 29);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void gen8_emit_chroma_key(struct intel_batchbuffer *batch, const int index)
+{
+	OUT_BATCH(GEN6_3DSTATE_CHROMA_KEY | (4 - 2));
+	OUT_BATCH(index << 30);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
+{
+	const int buffers = 33;
+	int i;
+
+	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS |
+		(((4 * buffers) + 1)- 2) /* DWORD count - 2 */);
+
+	for (i = 0; i < buffers; i++) {
+		OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT |
+			  GEN7_VB0_BUFFER_ADDR_MOD_EN);
+		OUT_BATCH(0); /* Address */
+		OUT_BATCH(0);
+		OUT_BATCH(0);
+	}
+}
+
+static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch)
+{
+	const int elements = 34;
+	int i;
+
+	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
+		(((2 * elements) + 1) - 2) /* DWORD count - 2 */);
+
+	/* Element 0 */
+	OUT_BATCH(VE0_VALID);
+	OUT_BATCH(
+		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+	/* Elements 1 -> 33 */
+	for (i = 1; i < elements; i++) {
+		OUT_BATCH(0);
+		OUT_BATCH(0);
+	}
+}
+
+static void gen8_emit_cc_state_pointers(struct intel_batchbuffer *batch)
+{
+	union {
+		float fval;
+		uint32_t uval;
+	} u;
+
+	unsigned offset;
+
+	u.fval = 1.0f;
+
+	offset = intel_batch_state_offset(batch, 64);
+	OUT_STATE(0);
+	OUT_STATE(0);      /* Alpha reference value */
+	OUT_STATE(u.uval); /* Blend constant color RED */
+	OUT_STATE(u.uval); /* Blend constant color BLUE */
+	OUT_STATE(u.uval); /* Blend constant color GREEN */
+	OUT_STATE(u.uval); /* Blend constant color ALPHA */
+
+	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS);
+	OUT_BATCH_STATE_OFFSET(offset | 1);
+}
+
+static void gen8_emit_blend_state_pointers(struct intel_batchbuffer *batch)
+{
+	unsigned offset;
+	int i;
+
+	offset = intel_batch_state_offset(batch, 64);
+
+	for (i = 0; i < 17; i++)
+		OUT_STATE(0);
+
+	OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
+	OUT_BATCH_STATE_OFFSET(offset | 1);
+}
+
+static void gen8_emit_ps_extra(struct intel_batchbuffer *batch)
+{
+        OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
+        OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID |
+		  GEN8_PSX_ATTRIBUTE_ENABLE);
+
+}
+
+static void gen8_emit_ps_blend(struct intel_batchbuffer *batch)
+{
+        OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
+        OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
+}
+
+static void gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer *batch)
+{
+	unsigned offset;
+
+	offset = intel_batch_state_offset(batch, 32);
+
+	OUT_STATE((uint32_t)0.0f); /* Minimum depth */
+	OUT_STATE((uint32_t)0.0f); /* Maximum depth */
+
+	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
+	OUT_BATCH_STATE_OFFSET(offset);
+}
+
+static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *batch)
+{
+	unsigned offset;
+	int i;
+
+	offset = intel_batch_state_offset(batch, 64);
+
+	for (i = 0; i < 16; i++)
+		OUT_STATE(0);
+
+	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP | (2 - 2));
+	OUT_BATCH_STATE_OFFSET(offset);
+}
+
+static void gen8_emit_primitive(struct intel_batchbuffer *batch)
+{
+        OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
+        OUT_BATCH(4);   /* gen8+ ignore the topology type field */
+        OUT_BATCH(1);   /* vertex count */
+        OUT_BATCH(0);
+        OUT_BATCH(1);   /* single instance */
+        OUT_BATCH(0);   /* start instance location */
+        OUT_BATCH(0);   /* index buffer offset, ignored */
+}
+
+static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) {
+	const unsigned offset = 0;
+	OUT_BATCH(GEN6_STATE_BASE_ADDRESS |
+		(19 - 2) /* DWORD count - 2 */);
+
+	/* general state base address - requires BB address
+	 * added to state offset to be stored in this location
+	 */
+	OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* stateless data port */
+	OUT_BATCH(0);
+
+	/* surface state base address - requires BB address
+	 * added to state offset to be stored in this location
+	 */
+	OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* dynamic state base address - requires BB address
+	 * added to state offset to be stored in this location
+	 */
+	OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* indirect state base address */
+	OUT_BATCH(BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* instruction state base address - requires BB address
+	 * added to state offset to be stored in this location
+	 */
+	OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* general state buffer size */
+	OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
+	/* dynamic state buffer size */
+	OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
+	/* indirect object buffer size */
+	OUT_BATCH(0x0 | BUFFER_SIZE_MODIFY);
+	/* intruction buffer size */
+	OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
+
+	/* bindless surface state base address */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	/* bindless surface state size */
+	OUT_BATCH(0);
+}
+
+/*
+ * Generate the batch buffer commands needed to initialize the 3D engine
+ * to its "golden state".
+ */
+int gen9_setup_null_render_state(struct intel_batchbuffer *batch)
+{
+	int ret;
+	int i;
+
+#define GEN8_PIPE_CONTROL_GLOBAL_GTT   (1 << 24)
+	/* PIPE_CONTROL */
+	OUT_BATCH(GEN6_PIPE_CONTROL |
+	         (6 - 2));	/* DWORD count - 2 */
+	OUT_BATCH(GEN8_PIPE_CONTROL_GLOBAL_GTT);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	/* PIPELINE_SELECT */
+	OUT_BATCH(GEN9_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+	gen8_emit_wm(batch);
+	gen8_emit_ps(batch);
+	gen8_emit_sf(batch);
+
+	OUT_CMD(GEN7_3DSTATE_SBE, 6); /* Check w/ Gen8 code */
+	OUT_CMD(GEN8_3DSTATE_SBE_SWIZ, 11);
+
+	gen8_emit_vs(batch);
+	gen8_emit_hs(batch);
+
+	OUT_CMD(GEN7_3DSTATE_GS, 10);
+	OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5);
+	OUT_CMD(GEN7_3DSTATE_DS, 11); /* Check w/ Gen8 code */
+	OUT_CMD(GEN6_3DSTATE_CLIP, 4);
+	gen8_emit_raster(batch);
+	OUT_CMD(GEN7_3DSTATE_TE, 4);
+	OUT_CMD(GEN8_3DSTATE_VF, 2);
+	OUT_CMD(GEN8_3DSTATE_WM_HZ_OP, 5);
+
+	/* URB States */
+	gen8_emit_urb(batch);
+
+	OUT_CMD(GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC, 4);
+	OUT_CMD(GEN8_3DSTATE_GATHER_POOL_ALLOC, 4);
+	OUT_CMD(GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 4);
+
+	/* Push Constants */
+	OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2);
+	OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2);
+	OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2);
+	OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2);
+	OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2);
+
+	/* Constants */
+	OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11);
+	OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11);
+	OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11);
+	OUT_CMD(GEN7_3DSTATE_CONSTANT_GS, 11);
+	OUT_CMD(GEN7_3DSTATE_CONSTANT_PS, 11);
+
+	OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3);
+	OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2);
+	gen8_emit_vf_topology(batch);
+
+	/* Streamer out declaration list */
+	gen8_emit_so_decl_list(batch);
+
+	/* Streamer out buffers */
+	for (i = 0; i < 4; i++) {
+		gen8_emit_so_buffer(batch, i);
+	}
+
+	/* State base addresses */
+	gen9_emit_state_base_address(batch);
+
+	OUT_CMD(GEN6_STATE_SIP, 3);
+	OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4);
+	OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
+
+	/* Chroma key */
+	for (i = 0; i < 4; i++) {
+		gen8_emit_chroma_key(batch, i);
+	}
+
+	OUT_CMD(GEN6_3DSTATE_LINE_STIPPLE, 3);
+	OUT_CMD(GEN6_3DSTATE_AA_LINE_PARAMS, 3);
+	OUT_CMD(GEN7_3DSTATE_STENCIL_BUFFER, 5);
+	OUT_CMD(GEN7_3DSTATE_HIER_DEPTH_BUFFER, 5);
+	OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3);
+	OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2);
+	OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2);
+	OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_OFFSET, 2);
+	OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_PATTERN, 1 + 32);
+	OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 1 + 16);
+	OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 1 + 16);
+	OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5);
+
+	/* Vertex buffers */
+	gen8_emit_vertex_buffers(batch);
+	gen8_emit_vertex_elements(batch);
+	OUT_CMD(GEN9_3DSTATE_COMPONENT_PACKING, 5);
+
+	OUT_BATCH(GEN6_3DSTATE_VF_STATISTICS | 1 /* Enable */);
+
+	gen8_emit_cc_state_pointers(batch);
+	gen8_emit_blend_state_pointers(batch);
+	gen8_emit_ps_extra(batch);
+	gen8_emit_ps_blend(batch);
+
+	/* 3D state sampler state pointers */
+	OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2);
+	OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2);
+	OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2);
+	OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2);
+	OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2);
+
+	OUT_CMD(GEN6_3DSTATE_SCISSOR_STATE_POINTERS, 2);
+
+	gen8_emit_viewport_state_pointers_cc(batch);
+	gen8_emit_viewport_state_pointers_sf_clip(batch);
+
+	/* 3D state binding table pointers */
+	OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, 2);
+	OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, 2);
+	OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, 2);
+	OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, 2);
+	OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, 2);
+
+	/* Launch 3D operation */
+	gen8_emit_primitive(batch);
+
+	OUT_BATCH(MI_BATCH_BUFFER_END);
+
+	return ret;
+}