summaryrefslogtreecommitdiff
path: root/target-mips/translate.c
AgeCommit message (Expand)AuthorFilesLines
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae1-0/+226
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae1-1/+2
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae1-21/+42
2015-06-12target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae1-6/+6
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-5/+15
2015-06-11target-mips: Misaligned memory accesses for MSAYongbok Kim1-10/+17
2015-06-11target-mips: Misaligned memory accesses for R6Yongbok Kim1-12/+27
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-150/+158
2015-06-11target-mips: move group of functions above gen_load_fpr32()Leon Alrae1-60/+58
2015-03-18target-mips: save cpu state before calling MSA load and store helpersLeon Alrae1-0/+2
2015-03-18target-mips: fix hflags modified in delay / forbidden slotLeon Alrae1-4/+15
2015-03-18target-mips: fix CP0.BadVAddr by stopping translation on Address ErrorLeon Alrae1-0/+1
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-47/+47
2015-02-13target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae1-1/+1
2015-02-13target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae1-2/+2
2015-02-13target-mips: fix detection of the end of the page during translationLeon Alrae1-1/+4
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-5/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-02-10target-mips: Clean up switch fall through after commit fecd264Markus Armbruster1-0/+4
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini1-10/+14
2014-12-16target-mips: convert single case switch into if statementLeon Alrae1-3/+1
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-0/+2
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki1-5/+14
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki1-9/+98
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki1-2/+6
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki1-0/+4
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki1-3/+3
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki1-1/+2
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki1-5/+8
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki1-1/+1
2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim1-5/+3
2014-11-07mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki1-1/+1
2014-11-07target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae1-0/+1
2014-11-07mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki1-2/+7
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim1-1/+48
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim1-0/+74
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim1-0/+113
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim1-0/+163
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim1-0/+118
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim1-0/+242
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim1-0/+88
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim1-0/+77
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim1-2/+80
2014-11-03target-mips: add MSA branch instructionsYongbok Kim1-114/+220
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim1-0/+56
2014-11-03target-mips: add MSA opcode enumYongbok Kim1-0/+245
2014-11-03target-mips: stop translation after ctc1Yongbok Kim1-0/+6
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae1-278/+260
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 04:37:36 +0000