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path: root/target-arm/translate-a64.c
AgeCommit message (Expand)AuthorFilesLines
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-8/+8
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell1-2/+2
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+13
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-9/+22
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell1-5/+86
2014-08-19target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell1-2/+3
2014-08-19target-arm: Fix return address for A64 BRK instructionsPeter Maydell1-1/+1
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+2
2014-06-19target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell1-1/+1
2014-06-19target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell1-1/+2
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell1-1/+44
2014-06-09target-arm: A64: Implement 3-register SHA instructionsPeter Maydell1-1/+58
2014-06-09target-arm: A64: Implement AES instructionsPeter Maydell1-1/+50
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell1-1/+53
2014-06-09target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell1-1/+1
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
2014-05-27target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias1-0/+4
2014-05-27target-arm: Move get_mem_index to translate.hEdgar E. Iglesias1-9/+0
2014-05-01target-arm: A64: Handle blr lrEdgar E. Iglesias1-1/+2
2014-05-01target-arm: implement WFE/YIELD as a yield for AArch64Rob Herring1-0/+6
2014-04-17target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée1-1/+1
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+3
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-0/+5
2014-04-17target-arm: A64: Add assertion that FP access was checkedPeter Maydell1-24/+51
2014-04-17target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell1-5/+295
2014-04-17target-arm: Add support for generating exceptions with syndrome informationPeter Maydell1-14/+35
2014-04-17target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell1-1/+7
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell1-0/+1
2014-03-24target-arm: Fix A64 Neon MLSPeter Maydell1-1/+1
2014-03-18target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée1-4/+105
2014-03-18target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée1-6/+45
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée1-6/+21
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell1-1/+19
2014-03-17target-arm: A64: Implement scalar saturating narrow opsAlex Bennée1-7/+28
2014-03-17target-arm: A64: Move handle_2misc_narrow functionAlex Bennée1-90/+90
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée1-3/+19
2014-03-17target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell1-2/+78
2014-03-17target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell1-0/+132
2014-03-17target-arm: A64: Implement FRINT*Peter Maydell1-3/+42
2014-03-17target-arm: A64: Implement SRIPeter Maydell1-8/+49
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée1-1/+69
2014-03-17target-arm: A64: List unsupported shift-imm opcodesPeter Maydell1-2/+11
2014-03-17target-arm: A64: Implement FCVTLPeter Maydell1-0/+47
2014-03-17target-arm: A64: Implement FCVTNPeter Maydell1-1/+23
2014-03-17target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell1-19/+169
2014-03-17target-arm: A64: Implement SHLL, SHLL2Peter Maydell1-1/+31
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell1-1/+74
2014-03-17target-arm: A64: Saturating and narrowing shift opsAlex Bennée1-3/+178
2014-03-17target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée1-1/+35
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