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AgeCommit message (Expand)AuthorFilesLines
2011-10-08target-alpha: Add high-resolution access to wall clock and an alarm.Richard Henderson4-4/+48
2011-10-08target-alpha: Implement HALT IPR.Richard Henderson3-0/+16
2011-10-08target-alpha: Implement WAIT IPR.Richard Henderson1-10/+21
2011-10-08target-alpha: Honor icount for RPCC instruction.Richard Henderson1-2/+10
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-4/+3
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-1/+1
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl3-4/+4
2011-07-30exec.h cleanupBlue Swirl2-40/+6
2011-07-20Fix unassigned memory access handlingBlue Swirl2-4/+7
2011-07-12target-alpha, target-ppc: Remove unnecessary setjmp.h includePeter Maydell1-2/+0
2011-06-26Remove exec-all.h include directivesBlue Swirl3-3/+0
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2-20/+22
2011-06-26exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl1-1/+1
2011-06-26cpu_loop_exit: avoid using AREG0Blue Swirl1-3/+3
2011-06-16alpha: remove unused variableMichael S. Tsirkin1-1/+6
2011-06-16alpha/translate: remve unused variablesMichael S. Tsirkin1-2/+1
2011-05-31target-alpha: Implement TLB flush primitives.Richard Henderson3-12/+34
2011-05-31target-alpha: Use a fixed frequency for the RPCC in system mode.Richard Henderson1-1/+10
2011-05-31target-alpha: Trap for unassigned and unaligned addresses.Richard Henderson2-1/+31
2011-05-31target-alpha: Remap PIO space for 43-bit KSEG for EV6.Richard Henderson1-3/+7
2011-05-31target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode.Richard Henderson2-4/+138
2011-05-31target-alpha: Implement more CALL_PAL values inline.Richard Henderson1-32/+108
2011-05-31target-alpha: Disable interrupts properly.Richard Henderson2-1/+16
2011-05-31target-alpha: All ISA checks to use TB->FLAGS.Richard Henderson2-181/+229
2011-05-31target-alpha: Swap shadow registers moving to/from PALmode.Richard Henderson3-2/+41
2011-05-31target-alpha: Implement do_interrupt for system mode.Richard Henderson1-10/+111
2011-05-31target-alpha: Add IPRs to be used by the emulation PALcode.Richard Henderson3-0/+124
2011-05-31target-alpha: Use kernel mmu_idx for pal_mode.Richard Henderson2-5/+9
2011-05-31target-alpha: Add various symbolic constants.Richard Henderson2-14/+44
2011-05-31target-alpha: Use do_restore_state for arithmetic exceptions.Richard Henderson1-19/+30
2011-05-31target-alpha: Tidy up arithmetic exceptions.Richard Henderson1-13/+21
2011-05-31target-alpha: Tidy exception constants.Richard Henderson3-26/+17
2011-05-31target-alpha: Enable the alpha-softmmu target.Richard Henderson1-0/+74
2011-05-31target-alpha: Rationalize internal processor registers.Richard Henderson5-559/+20
2011-05-31target-alpha: Merge HW_REI and HW_RET implementations.Richard Henderson3-22/+8
2011-05-31target-alpha: Cleanup MMU modes.Richard Henderson2-12/+32
2011-05-31target-alpha: Fix system store_conditionalRichard Henderson1-3/+3
2011-05-31target-alpha: Fix translation of PALmode memory insns.Richard Henderson3-183/+65
2011-05-31target-alpha: Remove partial support for palcode emulation.Richard Henderson3-38/+1
2011-05-31target-alpha: Single-step properly across branches.Richard Henderson1-15/+20
2011-04-20Remove unused function parameter from cpu_restore_stateStefan Weil1-1/+1
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil1-2/+1
2011-04-17softfloat: rename float*_eq() into float*_eq_quiet()Aurelien Jarno1-2/+2
2011-04-17target-alpha: use new float64_unordered_quiet() functionAurelien Jarno1-2/+3
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil1-3/+3
2011-03-13inline cpu_halted into sole callerPaolo Bonzini1-11/+0
2011-01-02softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()Peter Maydell1-1/+1
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-2/+1
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2-5/+5
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