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authorAnthony Liguori <aliguori@us.ibm.com>2013-02-18 08:37:29 -0600
committerAnthony Liguori <aliguori@us.ibm.com>2013-02-18 08:37:29 -0600
commit3c3adde005ec929d7d581d495d9a0bb223e6e055 (patch)
tree05d51a8fa7e87f9ed196b6926c3db84e56c41ca5 /target-sparc
parentf4c0f986c061f34fd5b020c30e2aa8c37e17193b (diff)
parent2d64255bd7c0d3933ff5ab2cabff11bcb09117a8 (diff)
Merge remote-tracking branch 'afaerber/qom-cpu' into staging
# By Andreas Färber # Via Andreas Färber * afaerber/qom-cpu: (47 commits) target-i386: Split command line parsing out of cpu_x86_register() target-i386: Move cpu_x86_init() target-lm32: Drop unused cpu_lm32_close() prototype target-s390x: Drop unused cpu_s390x_close() prototype spapr_hcall: Replace open-coded CPU loop with qemu_get_cpu() ppce500_spin: Replace open-coded CPU loop with qemu_get_cpu() e500: Replace open-coded loop with qemu_get_cpu() cpu: Add CPUArchState pointer to CPUState cputlb: Pass CPUState to cpu_unlink_tb() cpu: Move current_tb field to CPUState cpu: Move exit_request field to CPUState cpu: Move running field to CPUState cpu: Move host_tid field to CPUState target-cris: Introduce CRISCPU subclasses target-m68k: Pass M68kCPU to m68k_set_irq_level() mcf_intc: Pass M68kCPU to mcf_intc_init() mcf5206: Pass M68kCPU to mcf5206_init() target-m68k: Return M68kCPU from cpu_m68k_init() ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset() target-xtensa: Move TCG initialization to XtensaCPU initfn ...
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/cpu-qom.h2
-rw-r--r--target-sparc/cpu.c27
2 files changed, 24 insertions, 5 deletions
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
index 2a738ae360..89cd1cf2d3 100644
--- a/target-sparc/cpu-qom.h
+++ b/target-sparc/cpu-qom.h
@@ -38,6 +38,7 @@
/**
* SPARCCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A SPARC CPU model.
@@ -47,6 +48,7 @@ typedef struct SPARCCPUClass {
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} SPARCCPUClass;
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 4bc1afc755..ef52df6d74 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -114,15 +114,12 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model)
cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU));
env = &cpu->env;
- if (tcg_enabled()) {
- gen_intermediate_code_init(env);
- }
-
if (cpu_sparc_register(env, cpu_model) < 0) {
object_unref(OBJECT(cpu));
return NULL;
}
- qemu_init_vcpu(env);
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
@@ -851,12 +848,28 @@ void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n");
}
+static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ SPARCCPU *cpu = SPARC_CPU(dev);
+ SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
+
+ qemu_init_vcpu(&cpu->env);
+
+ scc->parent_realize(dev, errp);
+}
+
static void sparc_cpu_initfn(Object *obj)
{
+ CPUState *cs = CPU(obj);
SPARCCPU *cpu = SPARC_CPU(obj);
CPUSPARCState *env = &cpu->env;
+ cs->env_ptr = env;
cpu_exec_init(env);
+
+ if (tcg_enabled()) {
+ gen_intermediate_code_init(env);
+ }
}
static void sparc_cpu_uninitfn(Object *obj)
@@ -871,6 +884,10 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
{
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ scc->parent_realize = dc->realize;
+ dc->realize = sparc_cpu_realizefn;
scc->parent_reset = cc->reset;
cc->reset = sparc_cpu_reset;